* [libre-riscv-dev] [Bug 252] New: 3D accelerated opcodes need to be added to the POWER ISA simulator
@ 2020-03-13 15:36 bugzilla-daemon
0 siblings, 0 replies; only message in thread
From: bugzilla-daemon @ 2020-03-13 15:36 UTC (permalink / raw)
To: libre-riscv-dev
http://bugs.libre-riscv.org/show_bug.cgi?id=252
Bug ID: 252
Summary: 3D accelerated opcodes need to be added to the POWER
ISA simulator
Product: Libre Shakti M-Class
Version: unspecified
Hardware: PC
OS: Linux
Status: CONFIRMED
Severity: enhancement
Priority: ---
Component: Source Code
Assignee: lkcl@lkcl.net
Reporter: lkcl@lkcl.net
CC: libre-riscv-dev@lists.libre-riscv.org
NLnet milestone: ---
adding iterated support for 3D opcodes to ISA Simulator (and unit tests) is
needed. likely to be added to gem5.
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2020-03-13 15:36 [libre-riscv-dev] [Bug 252] New: 3D accelerated opcodes need to be added to the POWER ISA simulator bugzilla-daemon
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