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From: bugzilla-daemon@libre-riscv.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM
Date: Fri, 27 Mar 2020 10:44:30 +0000
Message-ID: <bug-268-13-RhBrMKruuY@http.bugs.libre-riscv.org/> (raw)
In-Reply-To: <bug-268-13@http.bugs.libre-riscv.org/>

http://bugs.libre-riscv.org/show_bug.cgi?id=268

Staf Verhaegen <staf@fibraservi.eu> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |staf@fibraservi.eu

--- Comment #1 from Staf Verhaegen <staf@fibraservi.eu> ---
I may have overlooked something and write-through may actually be implemented.
I think the trick is to have both a read and a write port; have these port
share the same address signal and also do a read when you do a write (e.g. have
transparent read port which make the read port always enabled).

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Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-27  9:50 [libre-riscv-dev] [Bug 268] New: " bugzilla-daemon
2020-03-27 10:44 ` bugzilla-daemon [this message]
2020-03-27 10:55 ` [libre-riscv-dev] [Bug 268] " bugzilla-daemon
2020-03-27 13:45 ` bugzilla-daemon
2020-03-27 16:05 ` bugzilla-daemon

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