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From: bugzilla-daemon@libre-riscv.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM
Date: Fri, 27 Mar 2020 13:45:23 +0000
Message-ID: <bug-268-13-87Ctu9oG1I@http.bugs.libre-riscv.org/> (raw)
In-Reply-To: <bug-268-13@http.bugs.libre-riscv.org/>

http://bugs.libre-riscv.org/show_bug.cgi?id=268

--- Comment #3 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> i think this was the basis of a unit test that jacob wrote, and he found that
> there was a definite bug in the nmigen Simulation.  i believe however it
> was a 2R1W arrangement.  jacob can you remember?

Found it:
https://salsa.debian.org/Kazan-team/simple-barrel-processor/-/blob/391d95f30bd99e37236af8fb95565809b7230e29/test/test_mem.py

nmigen bug:
https://github.com/m-labs/nmigen/issues/47

Turned out that write conflicts weren't implemented as advertised, the buggy
feature (write port priority) was later removed:
https://github.com/m-labs/nmigen/commit/a02e3750bfeba44bcaad4c5de8d9eb0ef055d9c6

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  parent reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-27  9:50 [libre-riscv-dev] [Bug 268] New: " bugzilla-daemon
2020-03-27 10:44 ` [libre-riscv-dev] [Bug 268] " bugzilla-daemon
2020-03-27 10:55 ` bugzilla-daemon
2020-03-27 13:45 ` bugzilla-daemon [this message]
2020-03-27 16:05 ` bugzilla-daemon

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