From: bugzilla-daemon@libre-riscv.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 272] functions needed in POWER simulator which match 3.0B spec
Date: Wed, 01 Apr 2020 18:40:43 +0000
Message-ID: <bug-272-13-hmh4GwNX22@http.bugs.libre-riscv.org/> (raw)
In-Reply-To: <bug-272-13@http.bugs.libre-riscv.org/>
http://bugs.libre-riscv.org/show_bug.cgi?id=272
--- Comment #13 from Michael Nolan <mtnolan2640@gmail.com> ---
I've got something in decoder/selectable_int.py. It uses Power's bit ordering
so it should be good for the compiler but something to be aware of if it's used
anywhere else.
I'm not sure what to do about left shift and right shift. Should SelectableInt
(0x10, bits=8) << 4 equal SelectableInt(0x100, bits=12) or SelectableInt(0x00,
bits=8)
It's also unsigned only, I'm not sure how much that matters right now
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Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 17:27 [libre-riscv-dev] [Bug 272] New: " bugzilla-daemon
2020-03-30 19:04 ` [libre-riscv-dev] [Bug 272] " bugzilla-daemon
2020-03-30 19:24 ` bugzilla-daemon
2020-03-31 12:57 ` bugzilla-daemon
2020-03-31 13:06 ` bugzilla-daemon
2020-03-31 14:24 ` bugzilla-daemon
2020-03-31 14:31 ` bugzilla-daemon
2020-03-31 18:35 ` bugzilla-daemon
2020-03-31 18:47 ` bugzilla-daemon
2020-03-31 20:06 ` bugzilla-daemon
2020-03-31 22:02 ` bugzilla-daemon
2020-03-31 23:07 ` bugzilla-daemon
2020-04-01 15:35 ` bugzilla-daemon
2020-04-01 18:40 ` bugzilla-daemon [this message]
2020-04-01 19:06 ` bugzilla-daemon
2020-04-01 21:55 ` bugzilla-daemon
2020-04-01 23:05 ` bugzilla-daemon
2020-04-01 23:44 ` bugzilla-daemon
2020-04-02 10:41 ` bugzilla-daemon
2020-04-05 18:37 ` bugzilla-daemon
[not found] <bug-272-13@https.bugs.libre-soc.org/>
2020-04-27 20:25 ` bugzilla-daemon
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