* [libre-riscv-dev] [Bug 282] New: investigate partially-generating unit tests from spec
@ 2020-04-05 20:29 bugzilla-daemon
0 siblings, 0 replies; only message in thread
From: bugzilla-daemon @ 2020-04-05 20:29 UTC (permalink / raw)
To: libre-riscv-dev
http://bugs.libre-riscv.org/show_bug.cgi?id=282
Bug ID: 282
Summary: investigate partially-generating unit tests from spec
Product: Libre-SOC's first SoC
Version: unspecified
Hardware: PC
OS: Linux
Status: CONFIRMED
Severity: enhancement
Priority: ---
Component: Source Code
Assignee: lkcl@lkcl.net
Reporter: lkcl@lkcl.net
CC: libre-riscv-dev@lists.libre-riscv.org
NLnet milestone: ---
michael, hi,
the PDF spec (and now the isa mdwn pages) contain the "format" of
the instruction:
opcode R1, R2, R3
we can therefore look at *using* that for template purposes, to create
an instruction to test.
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2020-04-05 20:29 [libre-riscv-dev] [Bug 282] New: investigate partially-generating unit tests from spec bugzilla-daemon
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