[libre-riscv-dev] [Bug 286] DataPointer concept: long-immediate references

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=286

--- Comment #7 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> (In reply to Jacob Lifshay from comment #5)
> > (In reply to Luke Kenneth Casson Leighton from comment #4)
> > >   particularly as a reduction in i-cache
> > > size obeys a square law reduction in power consumption.
> > 
> > I would expect the cache power usage to be linearly proportional to it's
> > size in bits once it's big enough to split into many smaller sram chunks,
> > since each sram chunk would use about the same power and you'd only need a
> > linear number of them.
> 
> whilst the cache power usage itself is linear (that being one dimension
> of the square effect), the increased size means that on loops you cannot
> fit as much code of the average loop *into* that cache, meaning that you
> end up with more L2 cache lookups.  this i believe is where the 2nd of
> the two dimensions of the square effect comes in.

I think you might be incorrect: increasing the size of the L1 cache should
increase hit rate which decreases the rate of accessing L2 and memory. Having a
bigger cache allows fitting more code into the cache, reducing the miss rate.
So, increasing the cache size would have a slightly less than linear increase
in power consumption due to decreasing L2 accesses.

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