[libre-riscv-dev] [Bug 292] New: implement multi-way read/write 6600 signals

[libre-riscv-dev] [Bug 292] New: implement multi-way read/write 6600 signals

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=292

            Bug ID: 292
           Summary: implement multi-way read/write 6600 signals
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

https://libre-soc.org/3d_gpu/architecture/6600scoreboard/600x-compunit_multi_rw.jpg
https://libre-soc.org/3d_gpu/architecture/6600scoreboard/600x-dependence_cell_multi_pending.jpg

the original 6600 scoreboard is single-signal request-ack protection
for multiple reads on the regfile.  overporting is then added so that
multiple batches of ALUs can simultaneously read (and write) to the
regfile.

we cannot do massive-way regfile porting.

additionally we need to do *different* regfiles for POWER: one of
these is the "Branch Control" Regfile, including CR0, CTR and other
conditional registers.

therefore it becomes more important to have fine-grain control over
the regfile, meaning that multiple go-read/req and go-write/req
wires are needed per FunctionUnit.

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[libre-riscv-dev] [Bug 292] implement multi-way read/write 6600 signals

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=292

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   budget (EUR) for|0                           |600
 completion of task|                            |
   (excludes budget|                            |
       allocated to|                            |
          subtasks)|                            |
    NLnet milestone|---                         |NLnet.2019.02

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[libre-riscv-dev] [Bug 292] implement multi-way read/write 6600 signals

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=292

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
    parent task for|                            |81
  budget allocation|                            |

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[libre-riscv-dev] [Bug 292] implement multi-way read/write 6600 signals

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=292

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|CONFIRMED                   |RESOLVED

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