* [libre-riscv-dev] [Bug 298] New: consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)
@ 2020-05-01 19:17 bugzilla-daemon
2020-05-01 23:21 ` [libre-riscv-dev] [Bug 298] " bugzilla-daemon
0 siblings, 1 reply; 2+ messages in thread
From: bugzilla-daemon @ 2020-05-01 19:17 UTC (permalink / raw)
To: libre-riscv-dev
https://bugs.libre-soc.org/show_bug.cgi?id=298
Bug ID: 298
Summary: consider using sum-addressed decoder in L1 cache
(maybe also L1 I cache)
Product: Libre-SOC's first SoC
Version: unspecified
Hardware: All
OS: All
Status: CONFIRMED
Severity: enhancement
Priority: ---
Component: Source Code
Assignee: lkcl@lkcl.net
Reporter: programmerjake@gmail.com
CC: libre-riscv-dev@lists.libre-riscv.org
NLnet milestone: ---
combines binary adder with address decoder, saving a few gate delays.
https://en.wikipedia.org/wiki/Sum-addressed_decoder
The patents appear to have expired.
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2020-05-01 19:17 [libre-riscv-dev] [Bug 298] New: consider using sum-addressed decoder in L1 cache (maybe also L1 I cache) bugzilla-daemon
2020-05-01 23:21 ` [libre-riscv-dev] [Bug 298] " bugzilla-daemon
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