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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags
Date: Mon, 18 May 2020 11:08:20 +0000
Message-ID: <bug-319-13-DKdmuY2Mpi@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-319-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=319

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
Section 3.2.2 Fixed-Point Exception Register (XER)

32 Summary Overflow (SO)
   The Summary Overflow bit is set to 1 when-
   ever an instruction (except mtspr and addex)
   sets the Overflow bit. Once set, the SO bit
   remains set until it is cleared by an mtspr
   instruction (specifying the XER). It is not
   altered by Compare instructions, or by other
   instructions (except mtspr to the XER and
   addex with operand CY=0) that cannot over-
   flow. Executing an mtspr instruction to the
   XER, supplying the values 0 for SO and 1 for
   OV, causes SO to be set to 0 and OV to be set
   to 1. addex does not alter the contents of SO.

33 Overflow (OV)
   The Overflow bit is set to indicate that an over-
   flow has occurred during execution of an
   instruction. The Overflow bit can also used as
   an independent Carry bit by using the addex
   with operand CY=0 instruction and avoiding
   other instructions that modify the Overflow bit
   (e.g., any XO-form instruction with OE=1).
   XO-form Add, Subtract From, and Negate
   instructions having OE=1 set it to 1 if the carry
   out of bit M is not equal to the carry out of bit
   M+1, and set it to 0 otherwise.

   XO-form Multiply Low and Divide instructions
   having OE=1 set it to 1 if the result cannot be
   represented in 64 bits (mulld, divd, divde,
   divdu, divdeu) or in 32 bits (mullw, divw,
   divwe, divwu, divweu), and set it to 0 other-
   wise.

   addex with operand CY=0 sets OV to 1 if there
   is a carry out of bit M, and sets it to 0 other-
   wise.

   The OV bit is not altered by Compare instruc-
   tions, or by other instructions (except mtspr to
   the XER) that cannot overflow.

34 Carry (CA)
   The Carry bit is set as follows, during execu-
   tion of certain instructions. Add Carrying, Sub-
   tract From Carrying, Add Extended, and
   Subtract From Extended types of instructions
   set it to 1 if there is a carry out of bit M, and
   set it to 0 otherwise. Shift Right Algebraic
   instructions set it to 1 if any 1-bits have been
   shifted out of a negative operand, and set it to
   0 otherwise. The CA bit is not altered by Com-
   pare instructions, or by other instructions
   (except Shift Right Algebraic, mtspr to the
   XER) that cannot carry.

44 Overflow32 (OV32)
   OV32 is set whenever OV is implicitly set, and
   is set to the same value that OV is defined to
   be set to in 32-bit mode.

45 Carry32 (CA32)
   CA32 is set whenever CA is implicitly set, and
   is set to the same value that CA is defined to
   be set to in 32-bit mode.

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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-18 11:04 [libre-riscv-dev] [Bug 319] New: " bugzilla-daemon
2020-05-18 11:08 ` bugzilla-daemon [this message]
2020-05-18 11:29 ` [libre-riscv-dev] [Bug 319] " bugzilla-daemon
2020-05-18 12:00 ` bugzilla-daemon
2020-05-18 16:13 ` bugzilla-daemon
2020-05-20  4:10 ` bugzilla-daemon
2020-05-20  4:50 ` bugzilla-daemon
2020-05-20 18:59 ` bugzilla-daemon

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