From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags
Date: Mon, 18 May 2020 16:13:57 +0000
Message-ID: <bug-319-13-QRq8J3Jv9b@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-319-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=319
Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:
What |Removed |Added
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Assignee|lkcl@lkcl.net |mtnolan2640@gmail.com
--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
michael could you convert all the outgoing XER fields to a Data record type?
this basically treating them just like spr1 2 3 which are Data type
what can then be done is, in the main_stage.py set the "ok" flag of carry32.ok
to 1 to indicate a *desire* to have the output_stage compute cr32 and so on.
each mainstage can then set those ok bits as needed.
some of those flags i think we might get already from the CSV files
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Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-18 11:04 [libre-riscv-dev] [Bug 319] New: " bugzilla-daemon
2020-05-18 11:08 ` [libre-riscv-dev] [Bug 319] " bugzilla-daemon
2020-05-18 11:29 ` bugzilla-daemon
2020-05-18 12:00 ` bugzilla-daemon
2020-05-18 16:13 ` bugzilla-daemon [this message]
2020-05-20 4:10 ` bugzilla-daemon
2020-05-20 4:50 ` bugzilla-daemon
2020-05-20 18:59 ` bugzilla-daemon
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