[libre-riscv-dev] [Bug 323] New: create POWER9 MUL pipeline

[libre-riscv-dev] [Bug 323] New: create POWER9 MUL pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=323

            Bug ID: 323
           Summary: create POWER9 MUL pipeline
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

a MUL pipeline is needed similar to the other pipelines in soc.fu, covering MUL
and MAC operations.

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[libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=323

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|lkcl@lkcl.net               |programmerjake@gmail.com
           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=305

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[libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=323

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
there are actually two different types of MUL here.

* VA Form - 3 int in, no carry/overflow
* X Form - usual style just like ALU/Logical

my feelings are mixed as that is a lot of ports if they are combined. still,
actuslly, after some thought it is the same (after combining) port allocation
as Shift.


# Multiply-Add High Doubleword VA-Form

VA-Form

* maddhd RT,RA.RB,RC

    prod[0:127] <- (RA) * (RB)
    sum[0:127] <- prod + EXTS(RC)
    RT <- sum[0:63]

Special Registers Altered:

    None

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[libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=323

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=a60febdeb1c572a4b85b410c6519383fc581732d

i moved mul operations over to a MUL Function Unit.  the unit test,
test_pipe_caller.py, when cookie-cut copied over, should then be changed:

                    fn_unit = yield pdecode2.e.fn_unit
                    self.assertEqual(fn_unit, Function.SHIFT_ROT.value)

to:

                    fn_unit = yield pdecode2.e.fn_unit
                    self.assertEqual(fn_unit, Function.MUL.value)

really we should look at some point at deriving a class to contain
the common code from all these tests, soc.fn.*.test.test_pipe_caller.py

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[libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=323

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
from microwatt: how to set up the inputs to the mul pipeline.  this can go in
main_stage.py when calling the mul unit:



if e_in.is_32bit = '1' then
    if e_in.is_signed = '1' then
        x_to_multiply.data1 <= (others => a_in(31));
        x_to_multiply.data1(31 downto 0) <= a_in(31 downto 0);
        x_to_multiply.data2 <= (others => b_in(31));
        x_to_multiply.data2(31 downto 0) <= b_in(31 downto 0);
    else
        x_to_multiply.data1 <= '0' & x"00000000" & a_in(31 downto 0);
        x_to_multiply.data2 <= '0' & x"00000000" & b_in(31 downto 0);
else
    if e_in.is_signed = '1' then
        x_to_multiply.data1 <= a_in(63) & a_in;
        x_to_multiply.data2 <= b_in(63) & b_in;
    else
        x_to_multiply.data1 <= '0' & a_in;
        x_to_multiply.data2 <= '0' & b_in;

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