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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline
Date: Wed, 10 Jun 2020 11:00:59 +0000
Message-ID: <bug-324-13-GgSoQKcQrz@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-324-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #8)
> Created the setup stage that translates from the input data to the format
> expected by DivPipeCore but didn't create tests yet, am going to be done for
> today. Still have to double check that I got the number of fractional bits
> correct.

fantastic.  as you can probably see i'm slowly going through the
test_pipe_caller.py code removing code-duplication.  for now i recommend
cookie-cutting fu/alu/test_pipe_caller.py in its entirety, because i
noticed that these use OE/Rc.  

* divdu RT,RA,RB (OE=0 Rc=0)

Special Registers Altered:

    CR0                     (if Rc=1)
    SO OV OV32             (if OE=1)

that means they're exactly like fixedarith, for *both* input and output
data, so you can straight-cookie-cut alu test_pipe_caller.py

i will drop in an fu/compunits/test/test_div_compunit.py

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  parent reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-19 12:03 [libre-riscv-dev] [Bug 324] New: " bugzilla-daemon
2020-05-19 12:04 ` [libre-riscv-dev] [Bug 324] " bugzilla-daemon
2020-05-19 12:16 ` bugzilla-daemon
2020-05-20  0:21 ` bugzilla-daemon
2020-05-22 21:03 ` bugzilla-daemon
2020-05-22 22:58 ` bugzilla-daemon
2020-05-26  3:55 ` bugzilla-daemon
2020-05-28  6:51 ` bugzilla-daemon
2020-05-28 10:03 ` bugzilla-daemon
2020-06-10  7:00 ` bugzilla-daemon
2020-06-10 11:00 ` bugzilla-daemon [this message]
2020-06-10 11:32 ` bugzilla-daemon
2020-06-10 18:29   ` Jacob Lifshay

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