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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline
Date: Tue, 19 May 2020 12:16:10 +0000
Message-ID: <bug-324-13-nGEztaKowV@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-324-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
register allocations, for fu.div.pipe_data.py

looks to be identical to ALUInputData and ALUOutputData.

https://libre-soc.org/openpower/isa/fixedarith/

# Divide

XO-Form   divw* RT,RA,RB

Special Registers Altered:

* CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
* SO OV OV32  (if OE=1)

# Modulo

X-Form  mod* RT,RA,RB

no special regs altered

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  parent reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-19 12:03 [libre-riscv-dev] [Bug 324] New: " bugzilla-daemon
2020-05-19 12:04 ` [libre-riscv-dev] [Bug 324] " bugzilla-daemon
2020-05-19 12:16 ` bugzilla-daemon [this message]
2020-05-20  0:21 ` bugzilla-daemon
2020-05-22 21:03 ` bugzilla-daemon
2020-05-22 22:58 ` bugzilla-daemon
2020-05-26  3:55 ` bugzilla-daemon
2020-05-28  6:51 ` bugzilla-daemon
2020-05-28 10:03 ` bugzilla-daemon
2020-06-10  7:00 ` bugzilla-daemon
2020-06-10 11:00 ` bugzilla-daemon
2020-06-10 11:32 ` bugzilla-daemon
2020-06-10 18:29   ` Jacob Lifshay

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