[libre-riscv-dev] [Bug 330] New: create POWER9 Logic Pipeline

[libre-riscv-dev] [Bug 330] New: create POWER9 Logic Pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=330

            Bug ID: 330
           Summary: create POWER9 Logic Pipeline
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

a pipeline is needed implementing
https://libre-soc.org/openpower/isa/fixedlogical/

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[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=330

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=305

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[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=330

Michael Nolan <mtnolan2640@gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|lkcl@lkcl.net               |mtnolan2640@gmail.com
                 CC|                            |mtnolan2640@gmail.com

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[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=330

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
i'm not seeing anything in main_stage.py that uses XER carry_in.  it appears
extraneous.  sticky overflow on the other hand, because carry can be generated,
should be.

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[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=330

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
michael i am just reviewing the isatables for LOGICAL operations.  two things
struck me:

1. CR0 is apparently an input for OP_CNTZ but not an output, and we have no cr0
in LogicalInputData.

2. i am not seeing any of the LOGICAL operations listed as needing carry in nor
producing carry out.

looking here:
https://libre-soc.org/openpower/isa/fixedlogical/

it does not appear that any or them set anything other than CR0 and that is an
output only.

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[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=330

--- Comment #3 from Michael Nolan <mtnolan2640@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> michael i am just reviewing the isatables for LOGICAL operations.  two
> things struck me:
> 
> 1. CR0 is apparently an input for OP_CNTZ but not an output, and we have no
> cr0 in LogicalInputData.

That's a mistake, fixing...

> 
> 2. i am not seeing any of the LOGICAL operations listed as needing carry in
> nor producing carry out.
> 
> looking here:
> https://libre-soc.org/openpower/isa/fixedlogical/
> 
> it does not appear that any or them set anything other than CR0 and that is
> an output only.

They shouldn't need carry no. 

BTW, did the logical pipe's output stage get replaced with common_output_stage?
The logical pipe test is broken and I'm not sure how to fix it.

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[libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=330

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Michael Nolan from comment #3)
> (In reply to Luke Kenneth Casson Leighton from comment #2)
> > michael i am just reviewing the isatables for LOGICAL operations.  two
> > things struck me:
> > 
> > 1. CR0 is apparently an input for OP_CNTZ but not an output, and we have no
> > cr0 in LogicalInputData.
> 
> That's a mistake, fixing...

ok excellent.  it didn't show up in the unit tests.

> > 
> > 2. i am not seeing any of the LOGICAL operations listed as needing carry in
> > nor producing carry out.
> > 
> > looking here:
> > https://libre-soc.org/openpower/isa/fixedlogical/
> > 
> > it does not appear that any or them set anything other than CR0 and that is
> > an output only.
> 
> They shouldn't need carry no. 

ok good to confirm.

> BTW, did the logical pipe's output stage get replaced with
> common_output_stage?

yes and common_input_stage as well.

> The logical pipe test is broken and I'm not sure how to
> fix it.

you might have been in between git pulls, can you try again?

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