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* [libre-riscv-dev] [Bug 331] New: Formal Correctness Proof for LOGICAL pipeline
@ 2020-05-20 15:20 bugzilla-daemon
  2020-05-20 15:20 ` [libre-riscv-dev] [Bug 331] " bugzilla-daemon
                   ` (9 more replies)
  0 siblings, 10 replies; 11+ messages in thread
From: bugzilla-daemon @ 2020-05-20 15:20 UTC (permalink / raw)
  To: libre-riscv-dev

https://bugs.libre-soc.org/show_bug.cgi?id=331

            Bug ID: 331
           Summary: Formal Correctness Proof for LOGICAL pipeline
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Formal Verification
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

a formal correctness proof is needed for the POWER9 Logical pipeline

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