[libre-riscv-dev] [Bug 339] create POWER9 ROTATE (SHIFTROT) pipeline

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=339

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|lkcl@lkcl.net               |mtnolan2640@gmail.com

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
michael, i need your help, here: sraw "works" in shift_rot/test_pipe_caller.py
only because carry isn't being checked in the test.  i'm not sure if it's
being set in the simulator?

* sraw RA,RS,RB (Rc=0)
* sraw.  RA,RS,RB (Rc=1)

    n <- (RB)[59:63]
    r <- ROTL32((RS)[32:63], 64-n)
    if (RB)[58] = 0 then
        m <-  MASK(n+32, 63)
    else m <- [0]*64
    s <- (RS)[32]
    RA <- r&m | ([s]*64)& ¬m
    carry <-  s & ((r&¬m)[32:63] != 0)
    CA    <-  carry
    CA32  <-  carry

Special Registers Altered:

    CA CA32
    CR0                    (if Rc=1)


* srawi RA,RS,SH (Rc=0)
* srawi.  RA,RS,SH (Rc=1)

    n <- SH
    r <- ROTL32((RS)[32:63], 64-n)
    m <- MASK(n+32, 63)
    s <- (RS)[32]
    RA <- r&m | ([s]*64)& ¬m
    carry <- s & ((r&¬m)[32:63] != 0)
    CA    <- carry
    CA32  <- carry

Special Registers Altered:

    CA CA32
    CR0                    (if Rc=1)

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