From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py
Date: Mon, 08 Jun 2020 14:28:11 +0000
Message-ID: <bug-369-13-VRSRc1zY3v@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-369-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=369
Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |mtnolan2640@gmail.com
--- Comment #3 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
in decoder/isa/caller.py does this look reasonable? it does seem to match
the hardware version (i am however seeing subf fail in test_core.py - am
assuming for now that this is a separate issue)
+ # OV (64-bit)
input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
output_sgn = exts(output.value, output.bits) < 0
ov = 1 if input_sgn[0] == input_sgn[1] and \
output_sgn != input_sgn[0] else 0
+ # OV (32-bit)
+ input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
+ output32_sgn = exts(output.value, 32) < 0
+ ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
+ output32_sgn != input32_sgn[0] else 0
+
self.spr['XER'][XER_bits['OV']] = ov
+ self.spr['XER'][XER_bits['OV32']] = ov32
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Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-08 1:09 [libre-riscv-dev] [Bug 369] New: " bugzilla-daemon
2020-06-08 13:50 ` [libre-riscv-dev] [Bug 369] " bugzilla-daemon
2020-06-08 14:10 ` bugzilla-daemon
2020-06-08 14:28 ` bugzilla-daemon [this message]
2020-06-08 17:57 ` bugzilla-daemon
2020-06-08 18:37 ` bugzilla-daemon
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