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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 369] New: missing XER SO/OV/32 check in test_pipe_caller.py
Date: Mon, 08 Jun 2020 01:09:26 +0000
Message-ID: <bug-369-13@https.bugs.libre-soc.org/> (raw)

https://bugs.libre-soc.org/show_bug.cgi?id=369

            Bug ID: 369
           Summary: missing XER SO/OV/32 check in test_pipe_caller.py
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/alu/test/test_pipe_caller.py;hb=HEAD

at least ALU and ShiftRot are misding so/ov/32 checking.

test_core.py shows some changes to the XER regfiles that appear not to be
correct, on execution of "adde."

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Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-08  1:09 bugzilla-daemon [this message]
2020-06-08 13:50 ` [libre-riscv-dev] [Bug 369] " bugzilla-daemon
2020-06-08 14:10 ` bugzilla-daemon
2020-06-08 14:28 ` bugzilla-daemon
2020-06-08 17:57 ` bugzilla-daemon
2020-06-08 18:37 ` bugzilla-daemon

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