[libre-riscv-dev] [Bug 369] New: missing XER SO/OV/32 check in test_pipe_caller.py

[libre-riscv-dev] [Bug 369] New: missing XER SO/OV/32 check in test_pipe_caller.py

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=369

            Bug ID: 369
           Summary: missing XER SO/OV/32 check in test_pipe_caller.py
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/alu/test/test_pipe_caller.py;hb=HEAD

at least ALU and ShiftRot are misding so/ov/32 checking.

test_core.py shows some changes to the XER regfiles that appear not to be
correct, on execution of "adde."

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[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=369

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
commit c822c90668e0fcac8d1717650408bce2c2dda353 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Mon Jun 8 14:50:35 2020 +0100

    added check which shows that OV32 in "adde." is not correct

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[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=369

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
-                comb += ov_o.data[0].eq((add_o[-2] != a[-1]) & (a[-1] ==
b[-1]))
-                comb += ov_o.data[1].eq((add_o[32] != a[31]) & (a[31] ==
b[31]))
+                # 32-bit (ov[1]) and 64-bit (ov[0]) overflow
+                ov = Signal(2, reset_less=True)
+                comb += ov[0].eq(calc_ov(a[-1], b[-1], ca[0], add_o[-2]))
+                comb += ov[1].eq(calc_ov(a[31], b[31], ca[1], add_o[32]))
+                comb += ov_o.data.eq(ov)

michael i believe the former code may have been incorrect, one of the tests
should have been using the carry (32/64) flags rather than the MSB of a?

also the OV32 handling in the simulator is missing, i will try to add
something.

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[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=369

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |mtnolan2640@gmail.com

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
in decoder/isa/caller.py does this look reasonable?  it does seem to match
the hardware version (i am however seeing subf fail in test_core.py - am
assuming for now that this is a separate issue)

+            # OV (64-bit)
             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
             output_sgn = exts(output.value, output.bits) < 0
             ov = 1 if input_sgn[0] == input_sgn[1] and \
                 output_sgn != input_sgn[0] else 0

+            # OV (32-bit)
+            input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
+            output32_sgn = exts(output.value, 32) < 0
+            ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
+                output32_sgn != input32_sgn[0] else 0
+
             self.spr['XER'][XER_bits['OV']] = ov
+            self.spr['XER'][XER_bits['OV32']] = ov32

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[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=369

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
found it.

--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -380,9 +380,8 @@ class ISACaller:
         carry_en = yield self.dec2.e.output_carry
         if carry_en:
             yield from self.handle_carry_(inputs, results, already_done)
-        ov_en = yield self.dec2.e.oe.oe
-        ov_ok = yield self.dec2.e.oe.ok
-        if ov_en & ov_ok:
+        ov_en = yield self.dec2.e.oe
+        if ov_en:

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[libre-riscv-dev] [Bug 369] missing XER SO/OV/32 check in test_pipe_caller.py

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=369

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|CONFIRMED                   |RESOLVED
         Resolution|---                         |FIXED

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
soc/simple/test/test_core.py now passes, with XER SO/OV/OV32 checking enabled.

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