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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 372] New: create cycle-accurate JIT-compiler-based processor simulator
Date: Tue, 09 Jun 2020 22:43:36 +0000
Message-ID: <bug-372-13@https.bugs.libre-soc.org/> (raw)

https://bugs.libre-soc.org/show_bug.cgi?id=372

            Bug ID: 372
           Summary: create cycle-accurate JIT-compiler-based processor
                    simulator
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: All
                OS: All
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: programmerjake@gmail.com
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

This could allow simulating our processor model much faster than most other
methods.

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Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-09 22:43 bugzilla-daemon [this message]
2020-06-09 22:44 ` [libre-riscv-dev] [Bug 372] " bugzilla-daemon
2020-06-09 22:46 ` bugzilla-daemon
2020-06-09 22:53 ` bugzilla-daemon
2020-06-09 23:17 ` bugzilla-daemon

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