[libre-riscv-dev] [Bug 372] New: create cycle-accurate JIT-compiler-based processor simulator

[libre-riscv-dev] [Bug 372] New: create cycle-accurate JIT-compiler-based processor simulator

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=372

            Bug ID: 372
           Summary: create cycle-accurate JIT-compiler-based processor
                    simulator
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: All
                OS: All
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: programmerjake@gmail.com
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

This could allow simulating our processor model much faster than most other
methods.

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[libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=372

Jacob Lifshay <programmerjake@gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|---                         |Low
           Assignee|lkcl@lkcl.net               |programmerjake@gmail.com
                 CC|                            |programmerjake@gmail.com

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[libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=372

--- Comment #1 from Jacob Lifshay <programmerjake@gmail.com> ---
this will likely need to happen after the october tapeout, if at all.

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[libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=372

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |lkcl@lkcl.net

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #0)
> This could allow simulating our processor model much faster than most other
> methods.

pearpc already contains both a JIT and a cycle-accurate mode.
there is also power-gem5 which was recently updated to be capable of
running a linux kernel (and the 500mb/sec memory leak fixed).

both of these are written in c / c++ and are extremely fast.

is there a compelling reason to, using an appropriate colloquialism,
"reinvent the wheel?"

(the main purpose of deliberately writing the simulator in python was to get
"working knowledge" handle on POWER9 internals: it's served that
purpose extremely well, and also very deliberately uses the exact same
POWER instruction decoder as used in the hardware)

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[libre-riscv-dev] [Bug 372] create cycle-accurate JIT-compiler-based processor simulator

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=372

--- Comment #3 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> (In reply to Jacob Lifshay from comment #0)
> > This could allow simulating our processor model much faster than most other
> > methods.
> 
> pearpc already contains both a JIT and a cycle-accurate mode.
> there is also power-gem5 which was recently updated to be capable of
> running a linux kernel (and the 500mb/sec memory leak fixed).
> 
> both of these are written in c / c++ and are extremely fast.
> 
> is there a compelling reason to, using an appropriate colloquialism,
> "reinvent the wheel?"

I haven't heard of a simulator that is cycle-accurate and JIT-compiled at the
same time, all the ones I've seen before are one or the other (perhaps
dynamically switchable) but not both simultaneously.

This bug report was mostly just to record my idea since it would be useful,
rather than a strict requirement.

This could be used to do things like run a few tens or hundreds of billions of
cycles on a fpga and check that the entire pipeline state matches the simulator
exactly -- unless the simulator is quite fast, that isn't very practical simply
because the existing simulators are too slow or not cycle-accurate.

This is like a bounded-cycle-count formal proof (icr the right term) except
that we can run it for millions or billions of times as many cycles.

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