From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 377] possible bug in Simulator Mem ld/st function
Date: Sat, 13 Jun 2020 23:52:09 +0000
Message-ID: <bug-377-13-2tUywheDyk@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-377-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=377
--- Comment #3 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
i think i got it.
nmigen memory write port, if you specify a granularity argument to cut the SRAM
into bytes, writes those bytes in *big* endian order.
however if you read the same interface with a single read-enable line, the
answer comes back in *little* endian order.
*face-palm*
i am however much preferring thinking in LE terms when it comes to memory
layouts and byte addressing.
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Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-12 14:58 [libre-riscv-dev] [Bug 377] New: " bugzilla-daemon
2020-06-12 14:58 ` [libre-riscv-dev] [Bug 377] " bugzilla-daemon
2020-06-12 15:27 ` bugzilla-daemon
2020-06-13 15:53 ` bugzilla-daemon
2020-06-13 23:52 ` bugzilla-daemon [this message]
2020-06-14 15:02 ` bugzilla-daemon
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