Libre RISC-V Mailing list Archives (accessible via public-inbox)
 help / color / Atom feed
From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 377] New: possible bug in Simulator Mem ld/st function
Date: Fri, 12 Jun 2020 14:58:35 +0000
Message-ID: <bug-377-13@https.bugs.libre-soc.org/> (raw)

https://bugs.libre-soc.org/show_bug.cgi?id=377

            Bug ID: 377
           Summary: possible bug in Simulator Mem ld/st function
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

michael, hi,

it looks like there might be a bug in caller.py Mem ld/st.  by accident
i asked a byte-store (stb) to write to address 0x9.  the memory-dump
(fu/compunits/test/test_compunit.py) dumps out the internal dictionary
(sim.mem.mem.items()) however it uses sim.mem.ld to initialise the
nmigen Memory object.

* bytes per word is 8
* address 9 divided by 8 is 1
* remainder is also 1.

does this mean that the LD/ST is being word-order realigned?


Writing 0xee to ST 0x9 memaddr 0x1/1
width,rem,shift,mask 1 1 0x30 0xff
mem @ 0x1: 0xabeeef0187654321
None
carry already done? 0b0
get_cu_outputs 2 0
after got outputs, rd_rel, wr_rel, wrmask:  0b0 0b0 0b0
busy 1
busy 1
busy 1
busy 0
check cu outputs stb 3, 1(2) {}
check extra output 'stb 3, 1(2)' 0 0
sim mem dump
         0 5432123412345678
         1 abeeef0187654321
         4 1828384822324252
nmigen mem dump
         0 5432123412345678
         1 abcdef018765ee21
         2 0000000000000000
         3 0000000000000000
         4 1828384822324252
         5 0000000000000000

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

             reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-12 14:58 bugzilla-daemon [this message]
2020-06-12 14:58 ` [libre-riscv-dev] [Bug 377] " bugzilla-daemon
2020-06-12 15:27 ` bugzilla-daemon
2020-06-13 15:53 ` bugzilla-daemon
2020-06-13 23:52 ` bugzilla-daemon
2020-06-14 15:02 ` bugzilla-daemon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=bug-377-13@https.bugs.libre-soc.org/ \
    --to=bugzilla-daemon@libre-soc.org \
    --cc=libre-riscv-dev@lists.libre-riscv.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Libre RISC-V Mailing list Archives (accessible via public-inbox)

Archives are clonable: git clone --mirror https://inbox.libre-soc.org/libre-riscv-dev

Example config snippet for mirrors


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git