[libre-riscv-dev] [Bug 382] New: nmigen wishbone Memory object needed

[libre-riscv-dev] [Bug 382] New: nmigen wishbone Memory object needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=382

            Bug ID: 382
           Summary: nmigen wishbone Memory object needed
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

for testing purposes (and also because we will actually need an on-board SRAM
and maybe a ROM as well) we need a means to place a Memory object behind a
wishbone bus.

does anyone know of anything like this?

one of the simplest ways to achieve it is to hack the minerva L1 cache
code, removing the "tag" aspect and substituting direct memory read-write.

however it would be preferable not to spend the time doing that if someone
knows of a pre-existing block.

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[libre-riscv-dev] [Bug 382] nmigen wishbone Memory object needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=382

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
found one

https://codecov.io/gh/m-labs/nmigen-soc/pull/6/diff?src=pr&el=tree#diff-bm1pZ2VuX3NvYy93aXNoYm9uZS9zcmFtLnB5

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[libre-riscv-dev] [Bug 382] nmigen wishbone Memory object needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=382

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
found one

https://codecov.io/gh/m-labs/nmigen-soc/pull/6/diff?src=pr&el=tree#diff-bm1pZ2VuX3NvYy93aXNoYm9uZS9zcmFtLnB5


https://github.com/m-labs/nmigen-soc/pull/6

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