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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability
Date: Sat, 06 Jun 2020 10:35:11 +0000
Message-ID: <bug-55-13-t9FaVKWnde@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-55-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=55

--- Comment #4 from Staf Verhaegen <staf@fibraservi.eu> ---
I want to add that also DDR signaling is left to be implemented in the logic
circuit on top of the level-shifted core output. It typically is done by using
both a rising edge and a falling edge triggered flip-flop on this output.

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  parent reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <bug-55-13@https.bugs.libre-soc.org/>
2020-06-05 17:59 ` bugzilla-daemon
2020-06-05 18:01 ` bugzilla-daemon
2020-06-06 10:26 ` bugzilla-daemon
2020-06-06 10:35 ` bugzilla-daemon [this message]
2020-06-06 11:03 ` bugzilla-daemon

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