[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability

[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=55

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
    NLnet milestone|Future                      |NLnet.2019.10.Cells
   budget (EUR) for|30000                       |0
 completion of task|                            |
   (excludes budget|                            |
       allocated to|                            |
          subtasks)|                            |

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[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=55

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
See 
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007699.html

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[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=55

--- Comment #3 from Staf Verhaegen <staf@fibraservi.eu> ---
The current IO cell design can be used to get most of the requirements. Some
clarification:

* There is a level shifted output from the external 3.3V pad voltage to an 1.8V
cell output to the core; this signal is asynchronous. It is meant that digital
logic is added on this output to implement things like meta-stability
prevention, debouncing and IRQ generation.
* The block has separate inputs for enabling each of the sink and the source
drivers. So if all drivers are disabled the output is high impedance and can
driven from an external driver; e.g. in this state the IO cell functions as an
input IO cell.
* There is a distinction between Schmidtt triggering and signal debouncing.
Schmidtt triggering means that the switching threshold is different for a
rising edge than for a falling edge. This is to avoid oscillation in the
level-shifted core output for slowly moving noisy input signals. With signal
debouncing typically stands for the filtering out of mutiple full swing signal
swings like one get from push buttons etc.
Current implementation of the level-shifting does not include Hysteresis but it
should be easy to add for the prototype. As said in first point thoough, signal
debouncing is left to the digital logic connected to the level-shifted output
of the IO cell.

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[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=55

--- Comment #4 from Staf Verhaegen <staf@fibraservi.eu> ---
I want to add that also DDR signaling is left to be implemented in the logic
circuit on top of the level-shifted core output. It typically is done by using
both a rising edge and a falling edge triggered flip-flop on this output.

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[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=55

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Staf Verhaegen from comment #4)
> I want to add that also DDR signaling is left to be implemented in the logic
> circuit on top of the level-shifted core output. It typically is done by
> using both a rising edge and a falling edge triggered flip-flop on this
> output.

this is fantastic, staf.  look forward to hearing how the test goes.

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