From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 70] evaluate Bus Architectures
Date: Wed, 20 May 2020 17:49:48 +0000
Message-ID: <bug-70-13-nTLc1XRi9q@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-70-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=70
--- Comment #13 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #12)
> (In reply to Jacob Lifshay from comment #11)
> > discovered that there are already quite a few protocols that are much more
> > widely used than omnixtend that support cache coherent memory access over a
> > network: google "rdma cache coherent"
>
> adding "wishbone" to that and opensparc T1 comes up
> https://www.oracle.com/technetwork/systems/opensparc/opensparc-internals-
book-1500271.pdf
neat! note that wishbone is not designed to run over ethernet or similar,
unlike most other rdma protocols.
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Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <bug-70-13@https.bugs.libre-soc.org/>
2020-05-11 21:19 ` bugzilla-daemon
2020-05-11 21:20 ` bugzilla-daemon
2020-05-20 6:47 ` bugzilla-daemon
2020-05-20 11:35 ` bugzilla-daemon
2020-05-20 17:49 ` bugzilla-daemon [this message]
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