[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=70

--- Comment #9 from Jacob Lifshay <programmerjake@gmail.com> ---
one interesting thing to investigate: can omnixtend run over wireguard? From my
initial research, ChaCha20 (one of the ciphers used) is implemented as a bunch
of binary adds, bitwise xors, and rotates, which seem quite easy to implement
in hardware assuming we only provide timing-attack resistance and *NOT*
power-attack resistance. The idea is that it would be resistant to attack over
the network and would use a well-tested protocol where we can use Linux's
network stack for testing purposes.

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[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=70

--- Comment #10 from Jacob Lifshay <programmerjake@gmail.com> ---
if we implemented omnixtend over wireguard, we would only need to implement
data packets in HW, relying on linux or some microcontroller to handle
connection keepalive, setup, teardown, etc.

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[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=70

--- Comment #11 from Jacob Lifshay <programmerjake@gmail.com> ---
discovered that there are already quite a few protocols that are much more
widely used than omnixtend that support cache coherent memory access over a
network: google "rdma cache coherent"

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[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=70

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #11)
> discovered that there are already quite a few protocols that are much more
> widely used than omnixtend that support cache coherent memory access over a
> network: google "rdma cache coherent"

adding "wishbone" to that and opensparc T1 comes up
https://www.oracle.com/technetwork/systems/opensparc/opensparc-internals-book-1500271.pdf

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[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=70

--- Comment #13 from Jacob Lifshay <programmerjake@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #12)
> (In reply to Jacob Lifshay from comment #11)
> > discovered that there are already quite a few protocols that are much more
> > widely used than omnixtend that support cache coherent memory access over a
> > network: google "rdma cache coherent"
> 
> adding "wishbone" to that and opensparc T1 comes up
> https://www.oracle.com/technetwork/systems/opensparc/opensparc-internals-
book-1500271.pdf

neat! note that wishbone is not designed to run over ethernet or similar,
unlike most other rdma protocols.

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