[libre-riscv-dev] daily kan-ban update 23may2020

[libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

yesterday / night / morning:

* converted pipeline input and output stages to "common code"
(soc.fu/*common*.py)
* removed some unnecessary inputs and outputs as a result, from the pipelines.
* created some more subset classes of Decode2ExecuteType
* helped Jean-Paul understand the FU-FU Matrices for coriolis2
* added ISEL to the Condition Register pipeline (including adding RB)
* implemented CR_ISEL unit test and formal proof (michael, you
duplicated the unit test)
* began to make MultiCompUnit understand "regspecs"
* documented where in MultiCompUnit that Cesar needs to put "zero_a"
support (and how to make it optional)
* added Michael's ssh key to the talos1 server
* gave it a name (talos1.libre-soc.org - good idea, Jacob)

today:

* create a page describing "regspecs"
* continue helping Cesar
* look out for incoming questions and commits
* watch at least 3 episodes from Season 4 of Stargate SG-1
* see if there's any recent Rick and Morty or Fast n Loud.

l.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Tobias Platen]

If no one else is working on the LDST unit I will start working there.
First I'll copy the skeleton files from another function unit, then I'll
try to implement the things described in the video L0 cache/buffer walkthrough [1].

[1] https://www.youtube.com/watch?v=6Yiyw4abJpE

On Sat, 23 May 2020 15:29:56 +0100
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

> yesterday / night / morning:
> 
> * converted pipeline input and output stages to "common code"
> (soc.fu/*common*.py)
> * removed some unnecessary inputs and outputs as a result, from the pipelines.
> * created some more subset classes of Decode2ExecuteType
> * helped Jean-Paul understand the FU-FU Matrices for coriolis2
> * added ISEL to the Condition Register pipeline (including adding RB)
> * implemented CR_ISEL unit test and formal proof (michael, you
> duplicated the unit test)
> * began to make MultiCompUnit understand "regspecs"
> * documented where in MultiCompUnit that Cesar needs to put "zero_a"
> support (and how to make it optional)
> * added Michael's ssh key to the talos1 server
> * gave it a name (talos1.libre-soc.org - good idea, Jacob)
> 
> today:
> 
> * create a page describing "regspecs"
> * continue helping Cesar
> * look out for incoming questions and commits
> * watch at least 3 episodes from Season 4 of Stargate SG-1
> * see if there's any recent Rick and Morty or Fast n Loud.
> 
> l.
> 
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> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev


-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

On Sat, May 23, 2020 at 3:56 PM Tobias Platen
<libre-soc@platen-software.de> wrote:
>
> If no one else is working on the LDST unit I will start working there.

good.  please however listen, pay attention, keep in constant
communication (do not wait until the end of the day if you are stuck,
like yesterday).

> First I'll copy the skeleton files from another function unit,

that will not be necessary: LDST is special-cased.  LDST is not
pipelined (they are FSMs), so virtually none of the infrastructure
there in soc.fu/* applies to it.

the reason why i created soc.fu.ldst.ldst_input_record is to make it
"consistent" when it comes to wiring up the Computation Units, which
will be dropped into soc/fu/{somefile.py} later.

> then I'll
> try to implement the things described in the video L0 cache/buffer walkthrough [1].

there are several pieces to this.  i need you to focus on them one at
a time, as this is particularly tricky.

first, a new class in soc/experiment/l0_cache.py is needed which
implements that core algorithm: the one that uses a PriorityPicker to
select one of the "active" LD/STs, then use that to OR-select an
output.

please assume the following inputs:

* an array of 8 Signals of length 8 bits which tell you which
addresses have matched against which other addresses.
  ( we call this the "address-match" array)
* an array of 8 Records containing {16 bytes data, 16 "enable" lines}

and the following output:

* a Record containing {16 bytes data, 16 "enable" lines}

in the address-match array, you want to find the first non-zero line.
once you have that index, use it to OR the 16 bytes and 16 "enables"
from the 8 records, into the output.

that's it.  it's quite simple, and is a crucial piece that we need.

i will cut/paste this into the appropriate bugreport (once i have found it).

please do *NOT* modify, replace or remove the existing L0CacheBuffer.
we need it, because it is currently in use.  it is not
high-performance, however it "works", and the rest of the code relies
on it.

l.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Cole Poirier]

Luke, since I am blocked on bpermd until Michael is able to take a look, and he is currently busy with the CR pipeline proofs, is there a new instruction I can work on implementing? Or tests that need to be written for existing modules that you’d like me to try doing? Essentially what tasks still need to be completed for the Oct 2020 prototype outside of the very technical and complex pieces like those that you, Michael, Jacob, Cesar, et al are focussing on? I realize that this information should be discernible from the wiki, bug reports and mailing list, however, due to my inexperience I’d like to ask for you guidance on what would be most helpful in achieving our goals for October.

Cole



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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Michael Nolan]

On 5/23/20 4:15 PM, Cole Poirier wrote:
> Luke, since I am blocked on bpermd until Michael is able to take a look, and he is currently busy with the CR pipeline proofs, is there a new instruction I can work on implementing? Or tests that need to be written for existing modules that you’d like me to try doing? Essentially what tasks still need to be completed for the Oct 2020 prototype outside of the very technical and complex pieces like those that you, Michael, Jacob, Cesar, et al are focussing on? I realize that this information should be discernible from the wiki, bug reports and mailing list, however, due to my inexperience I’d like to ask for you guidance on what would be most helpful in achieving our goals for October.
>
> Cole
>
>
>
> _______________________________________________
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I took a look at it earlier, but the test was broken because the input 
and output stages got deleted/moved, and I can't figure out what needs 
to be used to replace them.

--Michael.


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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

On Saturday, May 23, 2020, Michael Nolan <mtnolan2640@gmail.com> wrote:

>
> I took a look at it earlier, but the test was broken because the input and
> output stages got deleted/moved, and I can't figure out what needs to be
> used to replace them.


soc.fu they are now common base classes.  the code is exactly the same, it
is just split.

one weirdness, if you put a print statement on a and b, a is a signal, but
b ends up as an actual integer.

l.



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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Cole Poirier]

On May 23 2020, at 1:59 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> soc.fu they are now common base classes.  the code is exactly the
> same, it
> is just split.

I tried fixing this the naive way, by just substituting CommonInput
stageStage for LogicalInputStage but this results in the following error:

```
File "test_pipe_caller.py", line 193, in run_all
  m.submodules.alu = alu = LogicalBasePipe(pspec)
File "/home/colepoirier/src/soc/src/soc/fu/logical/pipeline.py", line
18, in __init__
  self.pipe1 = LogicalStages(pspec)
File "/home/colepoirier/src/nmutil/src/nmutil/dynamicpipe.py", line 37,
in __call__
 return super().__call__(*args, **kw)
File "/home/colepoirier/src/nmutil/src/nmutil/pipemodbase.py", line 34,
in __init__
  self.chain = self.get_chain()
File "/home/colepoirier/src/soc/src/soc/fu/logical/pipeline.py", line 9,
in get_chain
  inp = CommonInputStage(self.pspec)
TypeError: __init__() missing 1 required positional argument: 'modname'
```

Do I have to add something from fu/logical/logical_input_record.py, or
add something else in order to use CommonInputStage properly?


> one weirdness, if you put a print statement on a and b, a is a signal, but
> b ends up as an actual integer.

Are you referring to a and b of the CommonStage's or of another piece of code?

Cole


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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

On Sat, May 23, 2020 at 10:39 PM Cole Poirier <colepoirier@gmail.com> wrote:
>
> On May 23 2020, at 1:59 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> > soc.fu they are now common base classes.  the code is exactly the
> > same, it
> > is just split.
>
> I tried fixing this the naive way, by just substituting CommonInput
> stageStage for LogicalInputStage but this results in the following error:
>
> ```
> File "test_pipe_caller.py", line 193, in run_all

ok because you are running from "cd x.y.z" and then doing "python
./test_pipe_caller.py" i cannot tell which one of EIGHT
test_pipe_caller.py you are running.

l.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

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On Sat, May 23, 2020 at 10:39 PM Cole Poirier <colepoirier@gmail.com> wrote:
>
> On May 23 2020, at 1:59 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> > soc.fu they are now common base classes.  the code is exactly the
> > same, it
> > is just split.
>
> I tried fixing this the naive way, by just substituting CommonInput
> stageStage for LogicalInputStage

why?

look at the class:

class LogicalInputStage(CommonInputStage):
    def __init__(self, pspec):
        super().__init__(pspec, "input")   <---- must be initialised
with an argument, "input"

    def ispec(self):
        return LogicalInputData(self.pspec)   <--- CommonInputStage
does not have this

    def ospec(self):
        return LogicalInputData(self.pspec)   <---- CommonInputStage
does not have this

    def elaborate(self, platform):
        m = super().elaborate(platform) # covers A-invert, carry, excludes SO
        comb = m.d.comb
        ctx = self.i.ctx

        # operand b
        comb += self.o.b.eq(self.i.b)    <----   CommonInputStage does
not do this

        return m

so what you are trying to do is guaranteed to fail, on four separate counts.

* no initialisation of CommonInputStage 1st parameter
* no ispec
* no ospec
* parameter B will not be copied over

so, don't do that.

l.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

On Saturday, May 23, 2020, Cole Poirier <colepoirier@gmail.com> wrote:

> Luke, since I am blocked on bpermd until Michael is able to take a look,
> and he is currently busy with the CR pipeline proofs, is there a new
> instruction I can work on implementing? Or tests that need to be written
> for existing modules that you’d like me to try doing?


actually you could look at adding zero_a to op_sim in compalu_multi.  see
https://bugs.libre-soc.org/show_bug.cgi?id=336

it is 3am in brazil so Cesar will not be up, write on that bugreport when
you start and finish ok?

so in the morning he can take over again.

l.



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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Cole Poirier]

On May 23 2020, at 1:36 pm, Michael Nolan <mtnolan2640@gmail.com> wrote:
> I took a look at it earlier, but the test was broken because the input 
> and output stages got deleted/moved, and I can't figure out what needs 
> to be used to replace them.
> 
> --Michael.

On May 23 2020, at 1:57 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> actually you could look at adding zero_a to op_sim in compalu_multi.  see
> https://bugs.libre-soc.org/show_bug.cgi?id=336
> 
> it is 3am in brazil so Cesar will not be up, write on that bugreport when
> you start and finish ok?
> 
> so in the morning he can take over again.
> 
> l.

Thanks Luke and Michael. My plan for today then is to fix the tests for
the logical pipeline, then notify Michael of this task's completion on
the BPERM TODO bug report so he can take a look at what I've done wrong
in bpermd. After fixing the fu/logical/tests/test_pipe_caller.py, I will
work on adding zero_a to op_sim in compalu_multi on bug 336.

Cole

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Cesar Strauss]

On 05/23/2020 17:57, Luke Kenneth Casson Leighton escreveu:
> it is 3am in brazil so Cesar will not be up, write on that bugreport when
> you start and finish ok?

Something must have gone wrong somewhere...

It was only around 18:00 here, when you wrote that, not 03:00.

I'm on UTC-03:00.

Try:

$ TZ='America/Sao_Paulo' date

or, do "date -u" and subtract 3 hours.

Cheers,

Cesar

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

On Sat, May 23, 2020 at 11:08 PM Cesar Strauss <cestrauss@gmail.com> wrote:
>
> On 05/23/2020 17:57, Luke Kenneth Casson Leighton escreveu:
> > it is 3am in brazil so Cesar will not be up, write on that bugreport when
> > you start and finish ok?
>
> Something must have gone wrong somewhere...
>
> It was only around 18:00 here, when you wrote that, not 03:00.
>
> I'm on UTC-03:00.

ah!  i thought UTC +3, sorry!

ok Cole, let Cesar do the zero_imm unit test.

let me think what else to do.

l.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

$ python3 fu/logical/test/test_pipe_caller.py

succeeds.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

$
python3 fu/alu/test/test_pipe_caller.py

succeeds.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

 python3 fu/cr/test/test_pipe_caller.py

succeeds.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

python3 fu/shift_rot/test/test_pipe_caller.py

succeeds

(am i giving the clear message that the information "python
test_pipe_caller.py" is not enough, yet? :) )

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Cole Poirier]

On May 23 2020, at 3:17 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

> python3 fu/cr/test/test_pipe_caller.py

fu/logical/test/test_pipe_caller.py:

``
Traceback (most recent call last):
  File "test/test_pipe_caller.py", line 14, in <module>
    from soc.fu.logical.pipeline import LogicalBasePipe
  File "/home/colepoirier/src/soc/src/soc/fu/logical/pipeline.py", line
3, in <module>
    from soc.fu.logical.input_stage import LogicalInputStage
ModuleNotFoundError: No module named 'soc.fu.logical.input_stage'
```

Sorry I thought this was clear from: "Do I have to add something from
fu/logical/logical_input_record.py, or
add something else in order to use CommonInputStage properly?" I'll be
more explicit in the future.

Cole

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

On Sat, May 23, 2020 at 11:20 PM Cole Poirier <colepoirier@gmail.com> wrote:
>
> On May 23 2020, at 3:17 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
>
> > python3 fu/cr/test/test_pipe_caller.py
>
> fu/logical/test/test_pipe_caller.py:
>
> ``
> Traceback (most recent call last):
>   File "test/test_pipe_caller.py", line 14, in <module>
>     from soc.fu.logical.pipeline import LogicalBasePipe
>   File "/home/colepoirier/src/soc/src/soc/fu/logical/pipeline.py", line
> 3, in <module>
>     from soc.fu.logical.input_stage import LogicalInputStage
> ModuleNotFoundError: No module named 'soc.fu.logical.input_stage'
> ```

i missed that - that was what i needed.  so that was my fault, i've
added (and pushed) them now.

it should have been the first reaction. not to try to "fix" the
problem and then report an error in the method that you were trying to
fix the issue (that you didn't clearly state existed)

the very first thing should have been "report the original error".


> Sorry I thought this was clear from: "Do I have to add something from
> fu/logical/logical_input_record.py, or
> add something else in order to use CommonInputStage properly?"

not at all.

>  I'll be more explicit in the future.

always a good idea, and something that everyone forgets (including me).

l.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Cole Poirier]

On May 23 2020, at 3:27 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

> On Sat, May 23, 2020 at 11:20 PM Cole Poirier <colepoirier@gmail.com> wrote:
>> 
>> On May 23 2020, at 3:17 pm, Luke Kenneth Casson Leighton
>> <lkcl@lkcl.net> wrote:
>> 
>> > python3 fu/cr/test/test_pipe_caller.py
>> 
>> fu/logical/test/test_pipe_caller.py:
>> 
>> ``
>> Traceback (most recent call last):
>>   File "test/test_pipe_caller.py", line 14, in <module>
>>     from soc.fu.logical.pipeline import LogicalBasePipe
>>   File "/home/colepoirier/src/soc/src/soc/fu/logical/pipeline.py", line
>> 3, in <module>
>>     from soc.fu.logical.input_stage import LogicalInputStage
>> ModuleNotFoundError: No module named 'soc.fu.logical.input_stage'
>> ```
> 
> i missed that - that was what i needed.  so that was my fault, i've
> added (and pushed) them now.
> 
> it should have been the first reaction. not to try to "fix" the
> problem and then report an error in the method that you were trying to
> fix the issue (that you didn't clearly state existed)
> 
> the very first thing should have been "report the original error".

Learning. Will try to do this, but I expect to fail at least one more
time :)
 
>> Sorry I thought this was clear from: "Do I have to add something from
>> fu/logical/logical_input_record.py, or
>> add something else in order to use CommonInputStage properly?"
> 
> not at all.
> 
>>  I'll be more explicit in the future.
> 
> always a good idea, and something that everyone forgets (including me).
> 
> l.

Indeed. I'm trying to adapt to these new better habits of explicitness,
and the above 'explicitly state errors exist before doing something
fruitless/useless', but my old bad habits are clearly putting up a
fight. I will continue to try my best :)

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

On Sat, May 23, 2020 at 11:32 PM Cole Poirier <colepoirier@gmail.com> wrote:
> > the very first thing should have been "report the original error".
>
> Learning. Will try to do this, but I expect to fail at least one more
> time :)

:)

the immediate response to report the missing module can be easily
deduced from the workflow.

you *know* that people - everyone - should only commit code that
"works" (passes unit tests).  therefore, if someone commits code that
breaks, and it says "import module not found", you *know* that they
must have forgotten to commit a module.

.. yes?

easy, eh?

> Indeed. I'm trying to adapt to these new better habits of explicitness,
> and the above 'explicitly state errors exist before doing something
> fruitless/useless', but my old bad habits are clearly putting up a
> fight. I will continue to try my best :)

:)

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Cole Poirier]

On May 23 2020, at 3:14 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> On Sat, May 23, 2020 at 11:08 PM Cesar Strauss <cestrauss@gmail.com> wrote:
>> 
>> On 05/23/2020 17:57, Luke Kenneth Casson Leighton escreveu:
>> > it is 3am in brazil so Cesar will not be up, write on that
>> bugreport when
>> > you start and finish ok?
>> 
>> Something must have gone wrong somewhere...
>> 
>> It was only around 18:00 here, when you wrote that, not 03:00.
>> 
>> I'm on UTC-03:00.
> 
> ah!  i thought UTC +3, sorry!
> 
> ok Cole, let Cesar do the zero_imm unit test.
> 
> let me think what else to do.
> 
> l.

Will do! I'll await your directions.

Cole

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

On Sat, May 23, 2020 at 11:23 PM Cole Poirier <colepoirier@gmail.com> wrote:

> Will do! I'll await your directions.

ok so i sorted the missing files that i'd forgotten to commit.  that
unblocks (at least) 2 people from proceeding.  whew.  ok now what.

oh i know.  i got one.

can you look at soc/fu/compunits.py and add some extra imports which
create the following classes:

* BranchFunctionUnit
* ShiftRotFunctionUnit
etc. etc.

it should be blindingly obvious what to do.

should keep you occupied for all of ooo 5 minutes whilst i think.

l.

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Cole Poirier]

On May 23 2020, at 3:36 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> ok so i sorted the missing files that i'd forgotten to commit.  that
> unblocks (at least) 2 people from proceeding.  whew.  ok now what.
> 
> oh i know.  i got one.
> 
> can you look at soc/fu/compunits.py and add some extra imports which
> create the following classes:
> 
> * BranchFunctionUnit
> * ShiftRotFunctionUnit
> etc. etc.
> 
> it should be blindingly obvious what to do.
> 
> should keep you occupied for all of ooo 5 minutes whilst i think.

Woohoo! Finally finished a piece of code! I did the above and
commit-pushed it. Have a social function to attend to now, if you think
of something for me to do please post it here and I will try it in the morning.

Cole

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Re: [libre-riscv-dev] daily kan-ban update 23may2020

[Luke Kenneth Casson Leighton]

On Sat, May 23, 2020 at 11:59 PM Cole Poirier <colepoirier@gmail.com> wrote:
> > should keep you occupied for all of ooo 5 minutes whilst i think.
>
> Woohoo! Finally finished a piece of code!

aaawesome.

> I did the above and
> commit-pushed it. Have a social function to attend to now, if you think
> of something for me to do please post it here and I will try it in the morning.

enjoy.  willdo.

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