[libre-riscv-dev] daily kan-ban update 01jun2020

[libre-riscv-dev] daily kan-ban update 01jun2020

[Luke Kenneth Casson Leighton]

yesterday:

* got MultiCompUnit functional when interacting through the pipeline
API with the ALU that it manages.  (MultiCompUnit now qualifies as the
2nd or 3rd most complex piece of software engineering i've ever
tackled, in 30 years.  yes i keep a list.  with one exception, all of
the others involve SQL)
* got the ALU MultiCompUnit test working (found several bugs)
* got the Logical MultiCompUnit test working (found one bug)
* got the Condition Register MultiCompUnit test working (found two bugs)
* got the Branch Register MultiCompUnit test written

this morning:

* answered Marketnext about the upcoming Hackathon.  they got it
(which is great) - namely that the process we follow also applies to
Marketnext entrepreneurs just as much.
* got the Branch Register MultiCompUnit test working (swapped the
order of SPR1/SPR2)

today:

* Shift-Rot MCU (should be about 15 minutes)
* start looking at connecting MCUs to regfiles.

upcoming tasks (soon to be blockers) and blockers:

* TRAP, SPR and SYS pipelines (we need volunteers to work on these)
* MUL and DIV pipelines (Jacob)
* Interfaces for the 180nm ASIC.

l.

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Tobias Platen]

today:
working on formal verification of the datamerger class. 

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Cole Poirier]

Yesterday:

Started reading the materials on proofs provided by Luke and Cesar,
apologies, I should have communicated this on the bug report, however,
given that I was struggling I'm very grateful to Michael for taking it
over and finishing it. This, like Michael's fixing of proof_bpermd
really, really helps me learn because since I've already made several
attempts on my own(ish), I can see 'the path forward' to what I should
have done. I want to be able to contribute more than I currently am,
but, I'm realizing that unfortunately I have to learn to crawl before I
can walk then run. I've started the journey at least, and I learn many
new things every day.

Today:

If proof_regfile/Register is done, should I try writing
proof_regfile/Regfile? or if Michael is doing this, I volunteer to work
on TRAP and/or SYS instructions.

Cole


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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Luke Kenneth Casson Leighton]

On Mon, Jun 1, 2020 at 7:30 PM Cole Poirier <colepoirier@gmail.com> wrote:

> attempts on my own(ish), I can see 'the path forward' to what I should
> have done. I want to be able to contribute more than I currently am,
> but, I'm realizing that unfortunately I have to learn to crawl before I
> can walk then run.

you're braver than i am.  i can contribute small additions to proofs.

> I've started the journey at least, and I learn many
> new things every day.

:)

> Today:
>
> If proof_regfile/Register is done, should I try writing
> proof_regfile/Regfile? or if Michael is doing this, I volunteer to work
> on TRAP and/or SYS instructions.

TRAP, SYS and SPR are a higher priority at the moment.

l.

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Michael Nolan]

On 6/1/20 2:30 PM, Cole Poirier wrote:
> I want to be able to contribute more than I currently am,
> but, I'm realizing that unfortunately I have to learn to crawl before I
> can walk then run. I've started the journey at least, and I learn many
> new things every day.
Formal stuff is hard, it took me a while to figure out what I was doing 
when I first tried to learn it (back in 2016). Just keep trying, you'll 
eventually get it.
>
> Today:
>
> If proof_regfile/Register is done, should I try writing
> proof_regfile/Regfile? or if Michael is doing this, I volunteer to work
> on TRAP and/or SYS instructions.

I've got a proof for RegFileArray which shouldn't be too hard to modify 
for RegFile.


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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Luke Kenneth Casson Leighton]

On Mon, Jun 1, 2020 at 7:54 PM Michael Nolan <mtnolan2640@gmail.com> wrote:

> I've got a proof for RegFileArray which shouldn't be too hard to modify
> for RegFile.

go for it.  btw, just so you know: because the wen is unary,
RegFileArray technically can do broadcast (multiple bit-enables:
effectively VSPLAT), and ren (effectively) is an ORing of all enabled
bits.  i doubt however that we'll use broadcast-ren

if you've some time, i could really use your help on sraw, and also
"rlwinm." - the CR0 version of "rlwinm".
https://bugs.libre-soc.org/show_bug.cgi?id=339

l.

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Cole Poirier]

On Jun 1 2020, at 11:33 am, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> On Mon, Jun 1, 2020 at 7:30 PM Cole Poirier <colepoirier@gmail.com> wrote:
> 
>> attempts on my own(ish), I can see 'the path forward' to what I should
>> have done. I want to be able to contribute more than I currently am,
>> but, I'm realizing that unfortunately I have to learn to crawl before I
>> can walk then run.
> 
> you're braver than i am.  i can contribute small additions to proofs.

Thanks Luke, being with you on this perilous journey makes it much more
fun :)
 
>> I've started the journey at least, and I learn many
>> new things every day.
> 
> :)
> 
>> Today:
>> 
>> If proof_regfile/Register is done, should I try writing
>> proof_regfile/Regfile? or if Michael is doing this, I volunteer to work
>> on TRAP and/or SYS instructions.
> 
> TRAP, SYS and SPR are a higher priority at the moment.
> 
> l.

Should I work on the #TODOs in fu/trap/main_stage.py? Or is there
another file I should work on instead?

On Jun 1 2020, at 11:54 am, Michael Nolan <mtnolan2640@gmail.com> wrote:
>
> I've got a proof for RegFileArray which shouldn't be too hard to
> modify for RegFile.

Awesome! I'm excited to learn from it!

Cole

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Luke Kenneth Casson Leighton]

On Mon, Jun 1, 2020 at 8:03 PM Cole Poirier <colepoirier@gmail.com> wrote:

> Should I work on the #TODOs in fu/trap/main_stage.py?

go for it.  check the bugreport, discuss there
https://bugs.libre-soc.org/show_bug.cgi?id=325

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Cole Poirier]

Today (actual):

Spent today reading the parts of OPENPOWER ISA v3.1 related to traps,
not finished yet. I don't understand very much currently, but I think
that this will progress as I read and investigate further, however,
since I don't think I can read the spec well enough to understand what I
have to implement for fu/trap/main_stage, if someone else has the time I
think they should do it. Otherwise, I'll continue to work away at
understanding enough of the spec to be able to implement the trap pipeline.

Cole

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Jacob Lifshay]

On Mon, Jun 1, 2020, 03:41 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:

> * MUL and DIV pipelines (Jacob)
>

Working on that. Had some ISP-level internet issues yesterday, that's why
my build server went offline for a while in case anyone was wondering.

Jacob

>
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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Luke Kenneth Casson Leighton]

On Tue, Jun 2, 2020 at 1:23 AM Cole Poirier <colepoirier@gmail.com> wrote:
>
> Today (actual):
>
> Spent today reading the parts of OPENPOWER ISA v3.1 related to traps,
> not finished yet. I don't understand very much currently, but I think
> that this will progress as I read and investigate further, however,
> since I don't think I can read the spec well enough to understand what I
> have to implement for fu/trap/main_stage, if someone else has the time I
> think they should do it. Otherwise, I'll continue to work away at
> understanding enough of the spec to be able to implement the trap pipeline.

it is not in the least bit necessary to "understand" the spec.  i do not.

what *is* necessary is to understand how to translate microwatt VHDL
source code into nmigen.

and to TRUST that microwatt is correct.

this is why i have put in code-snippets from microwatt into the bugreport.

this turns an exercise that would take months if not years by a factor
of approximately TEN.

quotes understanding quotes comes later.

l.

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Luke Kenneth Casson Leighton]

On Tue, Jun 2, 2020 at 7:18 AM Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> On Mon, Jun 1, 2020, 03:41 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> wrote:
>
> > * MUL and DIV pipelines (Jacob)
> >
>
> Working on that.

good.  do bear in mind it's beginning to hold up development.  i'm
working round that.

as i explained to Cole: there are two ways to do development:

1) do everything yourself.  understand everything.  do everything from
first principles.  read every available piece of documentation.

2) find an existing implementation and translate it.

the first way takes months.  we do not have months.

the second way takes days to weeks.

so if you can pick up the pace significantly by working from microwatt
source code, and translating it to nmigen, that would be good.

> Had some ISP-level internet issues yesterday, that's why
> my build server went offline for a while in case anyone was wondering.

hmm that's interesting.  i cannot connect to gmail except by switching
off the HTTP proxy.  it would seem that this is a global world-wide
issue.

l.

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Cole Poirier]

On Jun 2 2020, at 3:11 am, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> On Tue, Jun 2, 2020 at 1:23 AM Cole Poirier <colepoirier@gmail.com> wrote:
>> 
>> Today (actual):
>> 
>> Spent today reading the parts of OPENPOWER ISA v3.1 related to traps,
>> not finished yet. I don't understand very much currently, but I think
>> that this will progress as I read and investigate further, however,
>> since I don't think I can read the spec well enough to understand
>> what I
>> have to implement for fu/trap/main_stage, if someone else has the
>> time I
>> think they should do it. Otherwise, I'll continue to work away at
>> understanding enough of the spec to be able to implement the trap pipeline.
> 
> it is not in the least bit necessary to "understand" the spec.  i do not.
> 
> what *is* necessary is to understand how to translate microwatt VHDL
> source code into nmigen.
> 
> and to TRUST that microwatt is correct.
> 
> this is why i have put in code-snippets from microwatt into the bugreport.
> 
> this turns an exercise that would take months if not years by a factor
> of approximately TEN.
> 
> quotes understanding quotes comes later.
> 
> l.

Aha! Thanks for this course correction Luke. I reviewed the comments on
the bug report yesterday, but I will now review it again with this fresh
knowledge, and get to work translating the microwatt VHDL into nmigen
for the trap pipeline.

Cole

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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Luke Kenneth Casson Leighton]

On Tuesday, June 2, 2020, Cole Poirier <colepoirier@gmail.com> wrote:

>
> Aha! Thanks for this course correction Luke. I reviewed the comments on
> the bug report yesterday, but I will now review it again with this fresh
> knowledge, and get to work translating the microwatt VHDL into nmigen
> for the trap pipeline.


it's basically a nobrainer, but still absolutely essential.

l.



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Re: [libre-riscv-dev] daily kan-ban update 01jun2020

[Cole Poirier]

On Jun 2 2020, at 4:03 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> it's basically a nobrainer, but still absolutely essential.
> 
> l.

Perfect :)

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