From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily status update 05may2020
Date: Tue, 5 May 2020 09:02:45 -0400
Message-ID: <1C547BD5-D8BF-42CF-872A-1A6BE039A156@gatech.edu> (raw)
In-Reply-To: <CAPweEDwbe8bVrqR9OpBYR-Xfp-K7XGi=YStbuF-s8jwU2z1O6w@mail.gmail.com>
> On May 5, 2020, at 6:47 AM, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
>
> yesterday i got the preliminary / testing L0CacheBuffer up and
> running:
Great!
> the important bit being the PortInterface class which
> connects to the LD/ST Computational Units.
>
What exactly is a LDSTCompUnit? A cursory Google search just brings up Libre-SOC.
Does it take a LD/ST instruction and compute the offset before access?
Why do you call it cache buffer - I’ve only heard the term cache.
Also, how many ways is the cache? Is it configureable - are you pulling in the source from minerva?
> today i'll be working on the redesigned LD/ST Computational Unit which
> has 3R-2W (indexed and update) capability.
> https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg <https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg>
Can we have a link to the gittree for this code.
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Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 10:47 Luke Kenneth Casson Leighton
2020-05-05 13:02 ` Yehowshua [this message]
2020-05-05 14:23 ` Luke Kenneth Casson Leighton
2020-05-05 13:07 ` Yehowshua
2020-05-05 14:24 ` Luke Kenneth Casson Leighton
2020-05-05 19:11 ` Tobias Platen
2020-05-05 21:55 ` Luke Kenneth Casson Leighton
2020-05-05 22:04 ` Michael Nolan
2020-05-05 22:53 ` Luke Kenneth Casson Leighton
2020-05-05 20:26 ` Michael Nolan
2020-05-05 22:00 ` Luke Kenneth Casson Leighton
2020-05-05 21:13 ` Cole Poirier
2020-05-05 22:03 ` Luke Kenneth Casson Leighton
2020-05-06 0:54 ` Cole Poirier
2020-05-06 1:24 ` Jacob Lifshay
2020-05-06 9:34 ` Luke Kenneth Casson Leighton
2020-05-06 13:00 ` Luke Kenneth Casson Leighton
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