From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily status update 05may2020
Date: Tue, 5 May 2020 11:47:32 +0100
Message-ID: <CAPweEDwbe8bVrqR9OpBYR-Xfp-K7XGi=YStbuF-s8jwU2z1O6w@mail.gmail.com> (raw)
i'm going to start doing daily status updates on the list,
"kanban-style". it would be good if everyone else did as well, as we
can keep in touch and see what's going on.
yesterday i got the preliminary / testing L0CacheBuffer up and
running: the important bit being the PortInterface class which
connects to the LD/ST Computational Units.
today i'll be working on the redesigned LD/ST Computational Unit which
has 3R-2W (indexed and update) capability.
https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
the L0CacheBuffer is on the critical path even for testing of the
LDSTCompUnit, because there are several LDSTCompUnits, all connecting
to the (one) L0CacheBuffer.
that's it. what is everyone else doing?
l.
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Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 10:47 Luke Kenneth Casson Leighton [this message]
2020-05-05 13:02 ` Yehowshua
2020-05-05 14:23 ` Luke Kenneth Casson Leighton
2020-05-05 13:07 ` Yehowshua
2020-05-05 14:24 ` Luke Kenneth Casson Leighton
2020-05-05 19:11 ` Tobias Platen
2020-05-05 21:55 ` Luke Kenneth Casson Leighton
2020-05-05 22:04 ` Michael Nolan
2020-05-05 22:53 ` Luke Kenneth Casson Leighton
2020-05-05 20:26 ` Michael Nolan
2020-05-05 22:00 ` Luke Kenneth Casson Leighton
2020-05-05 21:13 ` Cole Poirier
2020-05-05 22:03 ` Luke Kenneth Casson Leighton
2020-05-06 0:54 ` Cole Poirier
2020-05-06 1:24 ` Jacob Lifshay
2020-05-06 9:34 ` Luke Kenneth Casson Leighton
2020-05-06 13:00 ` Luke Kenneth Casson Leighton
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