From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily status update 05may2020
Date: Tue, 5 May 2020 23:53:59 +0100
Message-ID: <CAPweEDwtWMrkap385XEGJ3OySAvv+S82Jux5VUUq7C9igDci1w@mail.gmail.com> (raw)
In-Reply-To: <17a2f3a3-c0b3-d437-9ab2-01e67171c461@gmail.com>
On Tuesday, May 5, 2020, Michael Nolan <mtnolan2640@gmail.com> wrote:
> On 5/5/20 3:11 PM, Tobias Platen wrote:
>
>> Today I was mostly reading documentation for the add[o][.], subf[o][.],
>> adde*, subfe*, addze*, neg*, mullw*, divw* instructions that I will
>> implement tomorrow in the simulator.
>>
>
> Which simulator are we using now? There's internalop_sim.py and the
> autogenerated one in decoder/isa.
autogenerated. good catch michael. no need to implement code that already
exists.
unit tests need to be written for them however, to confirm that they work.
that funnily enough is more work as you have to test corner cases esp. on
carryin and out.
l.
--
---
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Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 10:47 Luke Kenneth Casson Leighton
2020-05-05 13:02 ` Yehowshua
2020-05-05 14:23 ` Luke Kenneth Casson Leighton
2020-05-05 13:07 ` Yehowshua
2020-05-05 14:24 ` Luke Kenneth Casson Leighton
2020-05-05 19:11 ` Tobias Platen
2020-05-05 21:55 ` Luke Kenneth Casson Leighton
2020-05-05 22:04 ` Michael Nolan
2020-05-05 22:53 ` Luke Kenneth Casson Leighton [this message]
2020-05-05 20:26 ` Michael Nolan
2020-05-05 22:00 ` Luke Kenneth Casson Leighton
2020-05-05 21:13 ` Cole Poirier
2020-05-05 22:03 ` Luke Kenneth Casson Leighton
2020-05-06 0:54 ` Cole Poirier
2020-05-06 1:24 ` Jacob Lifshay
2020-05-06 9:34 ` Luke Kenneth Casson Leighton
2020-05-06 13:00 ` Luke Kenneth Casson Leighton
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