[libre-riscv-dev] daily kan-ban update 02jun2020

[libre-riscv-dev] daily kan-ban update 02jun2020

[Luke Kenneth Casson Leighton]

yesterday:

* got Branch CompUnit test on par with its equivalent test_pipe_caller.py
* swapped RS from position "3" to position "1" (read port 1) on all Logical ops,
  OP_EXTS, and MTCRF
* started on ShiftRot CompUnit test.  fixed bugs, discovered that sraw is
  not setting CA/CA32, discovered that "rlwinm." is not implemented.
* fixed a bug in the CompUnit testing where the source operands were not
   zero'd.  ALUs picked up and used *old* operands (from a previous instruction)
* fixed two mask-related bugs in MultiCompUnit
* started on the linking of CompUnits to regfiles, through understanding of
   the relationship between CompUnits, regspecs, and Decode2Execute1Type.

today:

* getting Decode2Execute1Type to "understand" regspecs: to provide the
  "accessor" register information in the RegSpec API, so that it becomes
  dead simple to connect Decoder, CompUnits, and Regfiles.

l.

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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Tobias Platen]

today: more work on formal verification

currently I am trying to find out how to solve the following thing, I think it is a bug in nmigen.
Object (rec <unnamed> data en) cannot be used as a key in value collections

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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Tobias Platen]

On Tue, 2 Jun 2020 16:44:45 +0200
Tobias Platen <libre-soc@platen-software.de> wrote:

> today: more work on formal verification
> 
> currently I am trying to find out how to solve the following thing, I think it is a bug in nmigen.
> Object (rec <unnamed> data en) cannot be used as a key in value collections
This is now solved by upgrading nmigen.
> 
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Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Luke Kenneth Casson Leighton]

On Tue, Jun 2, 2020 at 4:03 PM Tobias Platen
<libre-soc@platen-software.de> wrote:
>
> On Tue, 2 Jun 2020 16:44:45 +0200
> Tobias Platen <libre-soc@platen-software.de> wrote:
>
> > today: more work on formal verification
> >
> > currently I am trying to find out how to solve the following thing, I think it is a bug in nmigen.
> > Object (rec <unnamed> data en) cannot be used as a key in value collections
> This is now solved by upgrading nmigen.

ah excellent!

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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Tobias Platen]

On Tue, 2 Jun 2020 16:37:33 +0100
Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

> On Tue, Jun 2, 2020 at 4:03 PM Tobias Platen
> <libre-soc@platen-software.de> wrote:
> >
> > On Tue, 2 Jun 2020 16:44:45 +0200
> > Tobias Platen <libre-soc@platen-software.de> wrote:
> >
> > > today: more work on formal verification
> > >
> > > currently I am trying to find out how to solve the following thing, I think it is a bug in nmigen.
> > > Object (rec <unnamed> data en) cannot be used as a key in value collections
> > This is now solved by upgrading nmigen.
I also found another bug in nmigen, that I will report soon. Just a two line fix.
> 
> ah excellent!
> 
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-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Luke Kenneth Casson Leighton]

On Tue, Jun 2, 2020 at 4:43 PM Tobias Platen
<libre-soc@platen-software.de> wrote:

> > > > Object (rec <unnamed> data en) cannot be used as a key in value collections
> > > This is now solved by upgrading nmigen.
> I also found another bug in nmigen, that I will report soon. Just a two line fix.

could you make sure to put links to both into #216, because otherwise
people will try to run the code, not realising that there's bugs, and
raise another bugreport?

l.

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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Jacob Lifshay]

today:

working on div and mul pipelines

helping explain Rust's Send and Sync traits:
https://github.com/PyO3/pyo3/pull/948#issuecomment-637108905

working some on requirements for Systemes Libres

Jacob
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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Luke Kenneth Casson Leighton]

On Tuesday, June 2, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:

> today:
>
> working on div and mul pipelines
>
> helping explain Rust's Send and Sync traits:
> https://github.com/PyO3/pyo3/pull/948#issuecomment-637108905


oo interesting


>
> working some on requirements for Systemes Libres
>
> Jacob
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>


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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Cole Poirier]

Today:

Translate microwatt vhdl code for trap pipeline into nmigen.

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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Luke Kenneth Casson Leighton]

On Wednesday, June 3, 2020, Cole Poirier <colepoirier@gmail.com> wrote:

> Today:
>
> Translate microwatt vhdl code for trap pipeline into nmigen.


brilliant.  should not take long.

l.



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Re: [libre-riscv-dev] daily kan-ban update 02jun2020

[Luke Kenneth Casson Leighton]

i created a link function between PowerDecode2 and the FunctionUnits, it's
not in use... yet.

however as part of that i made the regspec register names sufficiently
consistent so that they can be globally identified by PowerDecode2.

whilst doing that, i found that Branch can legitimately exit with zero
register file changes (branch not taken, no CTR mode, no LR mode).

that had to be fixed... in MultiCompUnit.

long day :)

l.





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