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From: "Immanuel, Yehowshua U" <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] next tasks
Date: Mon, 16 Mar 2020 18:30:15 +0000
Message-ID: <5CD6DF89-FF40-4732-9E42-1EB2092969B8@gatech.edu> (raw)
In-Reply-To: <CAC2bXD4nb6AA0Anc2w1Rf5f6c6CFXYbqOrD4WyszqZHXOcMZfw@mail.gmail.com>


If we decide we don't want rpython, then I would suggest Rust — I’ve

Like I’ve mentioned before, I’m all for Rust.
If I remember correctly, we’re implementing POWER 3.0 and Gem5 only has support for 2.7(2.7 and 3.0 - wow sounds like Python versions :)…

Anyways, one thing we should strongly consider making the simulator take advantage of multiple cores.

Honestly, we could implement a single cycle CPU in RTL and the compile it into C++ with Verilator.
To me, this seems to be the way to go.

1. Verilator Creates quite speedy cycle accurate C++ models
2. RTL is a really natural way to describe a CPU - duh
3. A single cycle CPU is about 3 - 4 days worth of labor
4. If we did the Single cycle CPU reference simulator in BSV for example, it’d simulate even faster than it would in verilator

I know using an RTL implementation of a CPU to test other RTL implementations seems unatural, but if we’d want to catch errors like pipeline and flushing behaviors in our CPU, then what makes more sense than a single cycle reference?

Also, I’d imagine in the future that we’d want to have speedy unit-testing etc etc, and considering ventilator offers multi-core support, we could see the speedup benefit of throwing our unit tests at a 64 core risen 3990x for example.

@Lauri, Jacob, and Luke - Thoughts and Comments?

Yehowshua
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  parent reply index

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CAPweEDyGztErPRa=9KLM9J02R1fLQ9Y23VY7UNAkfJ5yt-03PQ@mail.gmail.com>
     [not found] ` <20200220093921.635c47f72ea2faf85dd352b7@gmx.com>
2020-03-12 14:32   ` Hendrik Boom
2020-03-12 14:43     ` Luke Kenneth Casson Leighton
2020-03-12 17:40       ` Jacob Lifshay
2020-03-13  6:44         ` Lauri Kasanen
2020-03-13  7:38           ` Jacob Lifshay
2020-03-13  8:04             ` Lauri Kasanen
2020-03-13  8:25               ` Jacob Lifshay
2020-03-13 10:13                 ` Luke Kenneth Casson Leighton
2020-03-13 18:10                   ` [libre-riscv-dev] Rustup security Jacob Lifshay
2020-03-14 18:13                   ` [libre-riscv-dev] next tasks Hendrik Boom
2020-03-14 18:23                     ` whygee
2020-03-14 18:28                       ` Luke Kenneth Casson Leighton
2020-03-14 18:49                         ` whygee
2020-03-15  2:47                     ` [libre-riscv-dev] benefits of rust Jacob Lifshay
2020-03-15  5:18                       ` Hendrik Boom
2020-03-15  5:42                         ` Jacob Lifshay
2020-03-15  5:47                           ` [libre-riscv-dev] [OT] Minecraft garbage collection Hendrik Boom
2020-03-15  6:41                             ` Jacob Lifshay
2020-03-15 12:11                               ` Luke Kenneth Casson Leighton
2020-03-16 13:22                                 ` Luke Kenneth Casson Leighton
2020-03-16 16:22                                   ` Jacob Lifshay
2020-03-16 16:24                                     ` Luke Kenneth Casson Leighton
2020-03-17 18:23                   ` [libre-riscv-dev] next tasks Jacob Lifshay
2020-03-17 18:56                     ` Luke Kenneth Casson Leighton
2020-03-16 18:30         ` Immanuel, Yehowshua U [this message]
2020-03-16 18:51           ` Jacob Lifshay
2020-03-16 22:53             ` Luke Kenneth Casson Leighton
2020-03-16 22:53           ` Luke Kenneth Casson Leighton
2020-03-16 23:12             ` Immanuel, Yehowshua U
2020-03-16 23:16               ` Immanuel, Yehowshua U
2020-03-16 23:42               ` Luke Kenneth Casson Leighton

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