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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] next tasks
Date: Thu, 12 Mar 2020 14:43:30 +0000
Message-ID: <CAPweEDwHTi+VHrQ5n+KX98hCbVhDGey6U-LgPYe4H1w2WULG9w@mail.gmail.com> (raw)
In-Reply-To: <20200312143244.g6ns5j4am2jf3yhl@topoi.pooq.com>

On Thu, Mar 12, 2020 at 2:32 PM Hendrik Boom <hendrik@topoi.pooq.com> wrote:
>
> On Thu, Feb 20, 2020 at 09:39:21AM +0200, Lauri Kasanen wrote:
> > On Wed, 19 Feb 2020 14:14:16 +0000
> > Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> >
> > > we only have a few months in which to hang together all of the pieces
> > > that have been put together, to make a 64-bit 180nm chip.  because
> > > we're not doing this in verilog i believe it is reasonably doable, if
> > > we take steps to cut "unnecessary" things out i.e. not do too much.
> > > chop out L2 cache for example.
> >
> > What about the C/C++ simulator/interpreter timeline? It's not a blocker
> > for the hw tapeout, but it is a blocker for my work, which probably
> > mostly won't make it for the simple Oct tapeout anyway.

correct.  it's on a separate track.

> Or a simulation of the new SoC instruction set in C/C++?

to start from an existing power isa simulator (gem5 for example), that
simulator *happens* to be written in c or more likely c++, therefore
simulated vector and VPU instructions *have* to be written in c / c++.

otherwise we need to create - from scratch - an entire new POWER ISA
cycle-accurate instruction simulator, which would be a genuinely
stupid thing to spend time on given that there are a number of such
simulators in existence already.  including qemu.

l.

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Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CAPweEDyGztErPRa=9KLM9J02R1fLQ9Y23VY7UNAkfJ5yt-03PQ@mail.gmail.com>
     [not found] ` <20200220093921.635c47f72ea2faf85dd352b7@gmx.com>
2020-03-12 14:32   ` Hendrik Boom
2020-03-12 14:43     ` Luke Kenneth Casson Leighton [this message]
2020-03-12 17:40       ` Jacob Lifshay
2020-03-13  6:44         ` Lauri Kasanen
2020-03-13  7:38           ` Jacob Lifshay
2020-03-13  8:04             ` Lauri Kasanen
2020-03-13  8:25               ` Jacob Lifshay
2020-03-13 10:13                 ` Luke Kenneth Casson Leighton
2020-03-13 18:10                   ` [libre-riscv-dev] Rustup security Jacob Lifshay
2020-03-14 18:13                   ` [libre-riscv-dev] next tasks Hendrik Boom
2020-03-14 18:23                     ` whygee
2020-03-14 18:28                       ` Luke Kenneth Casson Leighton
2020-03-14 18:49                         ` whygee
2020-03-15  2:47                     ` [libre-riscv-dev] benefits of rust Jacob Lifshay
2020-03-15  5:18                       ` Hendrik Boom
2020-03-15  5:42                         ` Jacob Lifshay
2020-03-15  5:47                           ` [libre-riscv-dev] [OT] Minecraft garbage collection Hendrik Boom
2020-03-15  6:41                             ` Jacob Lifshay
2020-03-15 12:11                               ` Luke Kenneth Casson Leighton
2020-03-16 13:22                                 ` Luke Kenneth Casson Leighton
2020-03-16 16:22                                   ` Jacob Lifshay
2020-03-16 16:24                                     ` Luke Kenneth Casson Leighton
2020-03-17 18:23                   ` [libre-riscv-dev] next tasks Jacob Lifshay
2020-03-17 18:56                     ` Luke Kenneth Casson Leighton
2020-03-16 18:30         ` Immanuel, Yehowshua U
2020-03-16 18:51           ` Jacob Lifshay
2020-03-16 22:53             ` Luke Kenneth Casson Leighton
2020-03-16 22:53           ` Luke Kenneth Casson Leighton
2020-03-16 23:12             ` Immanuel, Yehowshua U
2020-03-16 23:16               ` Immanuel, Yehowshua U
2020-03-16 23:42               ` Luke Kenneth Casson Leighton

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