Re: [libre-riscv-dev] Introduction and Questions

From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Introduction and Questions
Date: Fri, 15 May 2020 14:45:09 -0400
Message-ID: <747F8870-06C6-46A0-AFD9-D55289D4C41A@gatech.edu> (raw)
In-Reply-To: <CAEoCstQz36UuDJ+ZUgLRJNeQkA=pTfYuzCr+XgF-FJY9+yJsvA@mail.gmail.com>

> On May 15, 2020, at 2:24 PM, Jeremy Singher <thejsingher@gmail.com> wrote:
> 
> Hi all,
> 
> My name is Jeremy Singher.

Hello and welcome!

> I'm a graduate student studying computer
> architecture, interested in open-source hardware and high performance
> microarchitectures. I am looking for an open-source hardware project I can
> contribute to through the course of my graduate studies, and I have some
> questions about the Libre-SOC project.
> 
> 1. It seems like you guys are building various components of an
> out-of-order microarchitecture, such as the scoreboard, and load-store
> ordering units. Do you have a complete microarchitecture diagram of the
> core (or a text description)?

Unfortunately, not yet - would you like to help with this?
We’re a bit starved on labor - about 4ish full-time in man-hours?

> I could find bits and pieces on specific
> components, but I'm interested in details like pipeline width, depth,
> branch-to-branch latency, load-use delay, etc.

We’re using a modification on the scoreboard architecture from the Cray CDC 6600.
Our scoreboard is somewhat similar to that of Tomasulo’s algorithm.

> 2. Is the SoC at a state at which I can evaluate performance on simple
> benchmarks in simulation? Other similar open-source hardware projects have
> make targets to launch verilator simulations, but I could not find an
> equivalent in your repos (although I probably am just bad at looking).

No. So since we’re implementing a POWER chip, we decided to start by writing a POWER
Simulator first. There are were a few options for this, QEMU, PearPC, and Gem5.

We’re making tweaks to PearPC and we also writing a simulator in Python that parses the official POWER3.0B spec.

I can’t remember why we decided to fiddle around with PearPC and not use QEMU or Gem5.

> 3. What is your target performance in terms of an established benchmark
> like Coremark, Dhrystone, Embench, or SPEC? I'm trying to compare the
> merits and progress of various hardware projects out-there.

From initial discussion, our first tapeout would be looking at Raspberry Pi rev B 2012 performance wise.
It would be good to get some drystone number down.

> 4. What is the right way to get started contributing? My experience is with
> Verilog, and I've looked at other languages too, including BSV and Chisel.
> I'm primarily interested in developing microarchitecture for
> performance-critical components, like branch predictors, prefetchers,
> instruction schedulers, and load-store units. Ideally, I could contribute
> my work as part of graduate studies to this project.
> 

Are you familiar with Python nMigen - its basically Chisel for Python. You mentioned michroarchitecture… Perhaps you could help Luke on the scoreboard.

Our codebase is a bit of a mess at the moment - there was so much to do for such a large project.
By August, with significant extra funding and labor in the pipeline, there should be more ability to clean things up.

> Sorry for the barrage of questions.
> 

No offense here :)

> Best,
> -Jeremy

Yehowshua

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