From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Introduction and Questions
Date: Sat, 16 May 2020 22:42:35 +0100
Message-ID: <CAPweEDz-4xfrM5wsjvcsxTpO53vMmJLDMpD24Qr2yZULurWz_g@mail.gmail.com> (raw)
In-Reply-To: <CAEoCstQLUzbeAyBBWE_FH8=AD78nd-qG8eAJo_cXaTG_Wz4ysQ@mail.gmail.com>
On Sat, May 16, 2020 at 9:34 PM Jeremy Singher <thejsingher@gmail.com> wrote:
> > Ok after some reflection I do see the most possible performance
> > difference in procedures calls. Most of the time in procedures some
> > scratch registers are pushed on the stack at entering.
>
> Its actually a performance difference on more cases than this. In the
> case of W R W R sequence to the same register, the second Write should
> be allowed to proceed before the first Write is executed, which also
> unblocks the second R.
in a strict historically-accurate 6600 (which we are not doing), it would block
at that 2nd W.
in the precise-augmented 6600-like design, the Operand Forwarding Bus
would provide the means for the second W to communicate the required
result to the 2nd R, allowing it to proceed, because Operand Forwarding
Buses provide the extra missing path that is not in the *original* 6600
that makes the register data paths functionally identical to a Common
Data Bus.
l.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
next prev parent reply index
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-15 18:24 Jeremy Singher
2020-05-15 18:45 ` Yehowshua
2020-05-15 19:15 ` Jeremy Singher
2020-05-15 19:20 ` Yehowshua
2020-05-15 19:24 ` Yehowshua
2020-05-15 19:33 ` Yehowshua
2020-05-15 20:11 ` Luke Kenneth Casson Leighton
2020-05-15 20:50 ` Jeremy Singher
2020-05-15 21:03 ` Yehowshua
2020-05-15 21:19 ` Jacob Lifshay
2020-05-15 21:55 ` Luke Kenneth Casson Leighton
2020-05-15 21:53 ` Luke Kenneth Casson Leighton
2020-05-15 22:15 ` Jeremy Singher
2020-05-15 22:29 ` Yehowshua
2020-05-15 22:51 ` Luke Kenneth Casson Leighton
2020-05-15 22:47 ` Luke Kenneth Casson Leighton
2020-05-15 23:49 ` Jeremy Singher
2020-05-16 0:40 ` Luke Kenneth Casson Leighton
2020-05-16 9:47 ` Staf Verhaegen
2020-05-16 11:30 ` Staf Verhaegen
2020-05-16 12:30 ` Luke Kenneth Casson Leighton
2020-05-16 20:34 ` Jeremy Singher
2020-05-16 21:42 ` Luke Kenneth Casson Leighton [this message]
2020-05-16 9:43 ` Staf Verhaegen
2020-05-16 12:14 ` Luke Kenneth Casson Leighton
2020-05-15 18:47 ` Yehowshua
2020-05-16 12:11 ` Luke Kenneth Casson Leighton
-- strict thread matches above, loose matches on Subject: below --
2020-05-15 6:50 Jeremy Singher
2020-06-06 22:47 ` Yehowshua
2020-06-06 22:48 ` Luke Kenneth Casson Leighton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAPweEDz-4xfrM5wsjvcsxTpO53vMmJLDMpD24Qr2yZULurWz_g@mail.gmail.com \
--to=lkcl@lkcl.net \
--cc=libre-riscv-dev@lists.libre-riscv.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Libre RISC-V Mailing list Archives (accessible via public-inbox)
Archives are clonable: git clone --mirror https://inbox.libre-soc.org/libre-riscv-dev
Example config snippet for mirrors
AGPL code for this site: git clone https://public-inbox.org/public-inbox.git