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From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] "simple" core
Date: Sun, 7 Jun 2020 20:27:22 -0400
Message-ID: <86EDE30A-FA1C-4248-8434-10FC28E7520E@gatech.edu> (raw)
In-Reply-To: <CAPweEDyVvef2FTsT6H-JU_6OoWd2UHDgLWJ9nLbPxqLEZ7d3Rg@mail.gmail.com>


> core.py really is *very* simple.  its execution model is as follows:
> 
> * receive instruction
> * decode instruction
> * identify through bitmasking which pipeline can handle it
> * enable *only* the MultiCompUnit managing that pipeline
> * wait for it to indicate that it is not busy (this includes regfile writing)
> * move on to the next instruction.


This is great to hear.
Keep up the great work.

Yehowshua
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  parent reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-07 23:31 Luke Kenneth Casson Leighton
2020-06-07 23:54 ` Cole Poirier
2020-06-07 23:58   ` Luke Kenneth Casson Leighton
2020-06-08  0:01     ` Cole Poirier
2020-06-08  0:06       ` Luke Kenneth Casson Leighton
2020-06-08  0:10         ` Cole Poirier
2020-06-08  0:27 ` Yehowshua [this message]
2020-06-08  0:35   ` Luke Kenneth Casson Leighton

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