From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] "simple" core
Date: Mon, 8 Jun 2020 00:58:26 +0100
Message-ID: <CAPweEDy2WS=_-7dbu3LGHBZxP7UgjDSthZBveahPHuSByyLE9g@mail.gmail.com> (raw)
In-Reply-To: <C4C83C38-D2A7-4531-9B36-CAEAED9181DF@getmailspring.com>
On Mon, Jun 8, 2020 at 12:54 AM Cole Poirier <colepoirier@gmail.com> wrote:
> > python3 soc/simple/test/test_core.py
>
> Just ran it. SO COOL!!
:)
i have to get LDSTCompUnit operational (the L0CacheBuffer memory
alignment), then i'm happier adding it in. right now it hangs if you
send it two instructions, for example - we can't have that as it would
stop core.py from working, as well.
> Looking forward to seeing this all come together as the rest has so far.
> And hopefully contributing a little :)
you already are! when you've added one instruction into the unit tests
for TRAP, that's basically (even with one instruction) when it can go
straight in. other tests can be added later.
l.
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Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-07 23:31 Luke Kenneth Casson Leighton
2020-06-07 23:54 ` Cole Poirier
2020-06-07 23:58 ` Luke Kenneth Casson Leighton [this message]
2020-06-08 0:01 ` Cole Poirier
2020-06-08 0:06 ` Luke Kenneth Casson Leighton
2020-06-08 0:10 ` Cole Poirier
2020-06-08 0:27 ` Yehowshua
2020-06-08 0:35 ` Luke Kenneth Casson Leighton
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