Re: [libre-riscv-dev] "simple" core

From: Cole Poirier <colepoirier@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] "simple" core
Date: Sun, 7 Jun 2020 16:54:21 -0700
Message-ID: <C4C83C38-D2A7-4531-9B36-CAEAED9181DF@getmailspring.com> (raw)
In-Reply-To: <CAPweEDyVvef2FTsT6H-JU_6OoWd2UHDgLWJ9nLbPxqLEZ7d3Rg@mail.gmail.com>

On Jun 7 2020, at 4:31 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

> the simple core is taking shape as a combination of all the pipelines,
> connected to the (5) types of register files.  all unit tests that
> have been developed to test *individual* pipelines have been borrowed
> through inheritance, to run against the register files, this time.
> you can try it out as:
> 
> python3 soc/simple/test/test_core.py

Just ran it. SO COOL!!

> the next phases will involve:
> 
> * adding in LDSTCompUnit
> * adding in minerva wishbone L1 I-Cache code (including bypass mode)
> * including the pre-written scoreboard "Instruction Queue" code
> * linking up NIA to the IQ, to fetch instructions and pass them to the decoder.
> 
> at that point we will have an actual core that is capable of executing
> instructions on its own.  after that, we have a basis for carrying out
> further code-morphs, to add the precise-capable augmented scoreboard
> and so on.
> 
> l.

Looking forward to seeing this all come together as the rest has so far.
And hopefully contributing a little :)

Cole

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