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From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Contributing to the Libre-Soc Project
Date: Sat, 6 Jun 2020 19:03:36 -0400
Message-ID: <8931BBAF-3BC2-43CD-BB7B-DD0AEAB17F2B@gatech.edu> (raw)
In-Reply-To: <CAE_rhwZK4FeFHDh4SNiUozji1vR1L4Xm=+BVBRuxHMw49CsMhQ@mail.gmail.com>



> On Jun 6, 2020, at 6:29 PM, Sanjay Menon <sanjayamenon.mec@gmail.com> wrote:
> 
> Hi,
> 
> I am a budding VLSI enthusiast and open-source developer. I would love to
> work with the team in your goal to achieve a completely open source project.
> 

My response will be quick as I spend my weekends writing my Master’s
Thesis.
Hi. And fantastic. We have a charter, that you should review here:
https://libre-soc.org/charter/ <https://libre-soc.org/charter/>

> I believe that as a beginner in this area, I would be able to learn more
> from you guys as I contribute to this wonderful project.

Sure. Would probably start by learning nMigen as it seems you’re coming
from a verilog background.

https://github.com/RobertBaruch/nmigen-tutorial <https://github.com/RobertBaruch/nmigen-tutorial>
http://blog.lambdaconcept.com/doku.php?id=nmigen:tutorial <http://blog.lambdaconcept.com/doku.php?id=nmigen:tutorial>


At the moment, we’re prepping for the Oct/Nov 2020 Tapeout.
Most of the work is going into hooking up the scoreboard to
our functional units right now.

We also make extensive use of formal verification.
Which reminds me, we need to separate FHDLTestCase class
into the nmutils repo since it's no longer officially maintained.

That’s a pretty simple task - maybe something you could handle.
You’ll know what I mean once you start playing with nMigen.

We also should start putting test we want to in `__init__.py` in the soc/tests
folder - so that `setup.py test` works.

So much to do, the aforementioned tasks are pretty beginner level.

> 
> I thank Yehowshua Immanuel for introducing me to this project. Can't wait
> to start already. Hoping to hear from you soon.
> 
> To know more about me do checkout my LinkedIn
> <http://www.linkedin.com/in/sanjay-menon-91791815a> profile.
> 
> Thanks and regards,
> Sanjay A Menon

Welcome,
	Yehowshua

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> libre-riscv-dev mailing list
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Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-06 22:29 Sanjay Menon
2020-06-06 23:03 ` Yehowshua [this message]
2020-06-06 23:15   ` [libre-riscv-dev] FHDLTestCase Luke Kenneth Casson Leighton
2020-06-06 23:22     ` Yehowshua
2020-06-06 23:27       ` Yehowshua
2020-06-06 23:45         ` Luke Kenneth Casson Leighton
2020-06-06 23:34       ` Luke Kenneth Casson Leighton
2020-06-06 23:45         ` Yehowshua
2020-06-06 23:49           ` Luke Kenneth Casson Leighton
2020-06-06 23:13 ` [libre-riscv-dev] Contributing to the Libre-Soc Project Luke Kenneth Casson Leighton

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