From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] FHDLTestCase
Date: Sun, 7 Jun 2020 00:49:12 +0100
Message-ID: <CAPweEDwu0UKr5FFiXQJ9_s_1rLjbpfgsWW_ceXnMXyU_vR81Lg@mail.gmail.com> (raw)
In-Reply-To: <E19BAAA1-A6B0-485F-BD25-26CB8A8E5ACB@gatech.edu>
On Sun, Jun 7, 2020 at 12:45 AM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> nMigen is in active development.
yehyeh.
> At somepoint, we may have to make nMigen a
> submodule frozen at a particular commit anyways.
when the ASIC layout is being done, this will be a hard requirement.
Jean-Paul explained that it is Industry Standard Practice to have full
reproducible builds, fully automated in all respects. not even the
username / login changes (nobody has separate usernames in the
repro-build scripts: even the username is exactly the same, added as
part of the OS clone/install script).
> We do have tests, so we’ll know when things start breaking.
yehyeh.
> We’ll take it one thing at a time.
:)
l.
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Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-06 22:29 [libre-riscv-dev] Contributing to the Libre-Soc Project Sanjay Menon
2020-06-06 23:03 ` Yehowshua
2020-06-06 23:15 ` [libre-riscv-dev] FHDLTestCase Luke Kenneth Casson Leighton
2020-06-06 23:22 ` Yehowshua
2020-06-06 23:27 ` Yehowshua
2020-06-06 23:45 ` Luke Kenneth Casson Leighton
2020-06-06 23:34 ` Luke Kenneth Casson Leighton
2020-06-06 23:45 ` Yehowshua
2020-06-06 23:49 ` Luke Kenneth Casson Leighton [this message]
2020-06-06 23:13 ` [libre-riscv-dev] Contributing to the Libre-Soc Project Luke Kenneth Casson Leighton
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