Re: [libre-riscv-dev] Contributing to the Libre-Soc Project

[Luke Kenneth Casson Leighton <lkcl@lkcl.net>]

(hi everyone please do cc sanjay as i've just manually approved this
message and he is not yet subscribed to the list, so would not see
replies unless explicitly cc'd.  sanjay, do subscribe to the list via
the interface at
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev)

On Sat, Jun 6, 2020 at 11:47 PM Sanjay Menon <sanjayamenon.mec@gmail.com> wrote:
>
> Hi,
>
> I am a budding VLSI enthusiast and open-source developer. I would love to
> work with the team in your goal to achieve a completely open source project.

good to hear from you.

one key thing to appreciate: this is a libre project, not an "open
source" one.  the distinction is not immediately apparent or
well-known to people, and it comes down to this: a Libre project says
"no" when it comes to unethical practices, whereas an "open" one makes
no such declaration.  "open source" projects *might* have people
contributing to it with the very best of intentions, however none of
them will have *actively* declared not to cross an ethical line.

> I believe that as a beginner in this area, I would be able to learn more
> from you guys as I contribute to this wonderful project.

well, one thing i love telling people the story is of how Cole Poirier
has gone from zero hardware knowledge to writing his own nmigen
modules.  so there is room for everyone with all levels of experience.

> I thank Yehowshua Immanuel for introducing me to this project. Can't wait
> to start already. Hoping to hear from you soon.

so, congratulations on the first step - getting in touch (*tick*) :)
just go through the list on the "how can i help as a developer", in
your own time - https://libre-soc.org/

in particular you'll find the development workflow advice here:
https://libre-soc.org/HDL_workflow/

this is a combined page of best practices for collaboration, as well
as containing developer-style "getting started" instructions.


> To know more about me do checkout my LinkedIn
> <http://www.linkedin.com/in/sanjay-menon-91791815a> profile.

nice, i see you've done actual VLSI layout - we're using coriolis2,
this involves actually writing the layout *entirely as a python
program*:
https://bugs.libre-soc.org/buglist.cgi?quicksearch=coriolis2&list_id=826

if you'd like to do that, you're more than welcome (and can receive
donations from NLNet for doing so).  there's plenty of other tasks as
well.

you have some cool projects on there, including implementing SHA256 in
hardware: did you do that at gate-level or in an HDL?

best,

l.

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