[libre-riscv-dev] [Bug 336] New: add indicator to Decode2ExecuteType that RA is zero
2020-05-24 3:33 UTC (16+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
[libre-riscv-dev] [Bug 343] New: compalu_multi write requests need to hook into Data.ok
2020-05-24 3:33 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok "
[libre-riscv-dev] Fwd: [OpenPOWER-HDL-Cores] POWER9 ISA opcode usage statistics
2020-05-24 1:01 UTC - mbox.gz / Atom
[libre-riscv-dev] [Bug 342] New: formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
2020-05-23 23:17 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed "
[libre-riscv-dev] daily kan-ban update 23may2020
2020-05-23 23:01 UTC (25+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 341] New: unit tests needed for soc.fu.compunits (shared with soc.fu.*/test_pipe_caller.py)
2020-05-23 22:58 UTC (3+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 341] unit tests needed for soc.fu.compunits (shared with soc.fu.*/test_pipe_caller.py) "
[libre-riscv-dev] [Bug 316] New: bperm TODO
2020-05-23 22:35 UTC (20+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 316] bperm TODO "
[libre-riscv-dev] [Bug 314] New: Create Condition Register pipeline
2020-05-23 21:01 UTC (7+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline "
[libre-riscv-dev] [Bug 332] New: Formal correctness proof needed for CR pipeline
2020-05-23 18:43 UTC (7+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline "
[libre-riscv-dev] Function Units "patch-up" linking to Comp Unit code
2020-05-23 18:23 UTC - mbox.gz / Atom
[libre-riscv-dev] daily kan-ban update 22may2020
2020-05-23 18:16 UTC (16+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
2020-05-23 15:23 UTC (2+ messages) - mbox.gz / Atom
[libre-riscv-dev] Priority Encoder for Cesar
2020-05-23 14:21 UTC (2+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 313] New: Create Branch Pipeline for POWER9
2020-05-23 3:06 UTC (11+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9 "
[libre-riscv-dev] dns entries for talos server & server maintenance
2020-05-23 2:46 UTC (6+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 324] New: create POWER9 DIV pipeline
2020-05-22 22:58 UTC (3+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline "
[libre-riscv-dev] [Bug 195] Formal correctness framework is needed for Power ISA
2020-05-22 20:31 UTC (3+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 340] New: formal proof of POWER9 SHIFTROT pipeline needed
2020-05-22 20:31 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed "
[libre-riscv-dev] [Bug 339] New: create POWER9 ROTATE pipeline
2020-05-22 19:07 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 339] create POWER9 ROTATE pipeline "
[libre-riscv-dev] [Bug 335] New: Formal Correctness Proof for Branch pipeline
2020-05-22 19:00 UTC (10+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline "
[libre-riscv-dev] [Bug 330] New: create POWER9 Logic Pipeline
2020-05-22 18:38 UTC (5+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline "
[libre-riscv-dev] [Bug 305] New: Create Pipelined ALU similar to alu_hier.py
2020-05-22 17:27 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py "
[libre-riscv-dev] [Bug 338] New: CompUnitALU needs go_die to be wired to ALU shadow mask
2020-05-22 16:17 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 338] CompUnitALU needs go_die to be wired to ALU shadow mask "
[libre-riscv-dev] [Bug 329] New: coriolis2 experiment layout for Dependency Matrices
2020-05-22 13:53 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices "
[libre-riscv-dev] [Bug 333] New: investigate why CR pipeline code took 100% CPU and locked up generating ILANG
2020-05-22 13:49 UTC (24+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG "
[libre-riscv-dev] daily kan-ban update 21may2020
2020-05-21 21:58 UTC (10+ messages) - mbox.gz / Atom
` [libre-riscv-dev] openpower meeting starting shortly
[libre-riscv-dev] [Bug 307] New: look at installing a kan-ban board on top of bugzilla
2020-05-21 21:12 UTC (3+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla "
[libre-riscv-dev] [Bug 337] New: Convention for register outputs in *OutputData structures is to use "Data"
2020-05-21 20:12 UTC - mbox.gz / Atom
[libre-riscv-dev] [Bug 318] New: fix LDSTCompUnit
2020-05-21 17:55 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 318] fix LDSTCompUnit "
[libre-riscv-dev] [Bug 328] New: move decoder RB exts function into nmutil
2020-05-21 17:48 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 328] move decoder RB exts function into nmutil "
[libre-riscv-dev] [Bug 334] New: POWER decode A=zero needs to be set as a flag in Execute1Type
2020-05-21 16:48 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 334] POWER decode A=zero needs to be set as a flag in Execute1Type "
[libre-riscv-dev] [Bug 331] New: Formal Correctness Proof for LOGICAL pipeline
2020-05-21 13:01 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline "
[libre-riscv-dev] [Bug 306] New: Formal Correctness Proof for ALU pipeline
2020-05-21 13:01 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline "
[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
2020-05-21 13:01 UTC - mbox.gz / Atom
[libre-riscv-dev] [Bug 304] New: Define minimum viable interface set for 180nm ASIC
2020-05-20 22:14 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC "
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