[libre-riscv-dev] [Bug 353] New: formal proof of soc.regfile classes RegFile and RegFileArray needed
2020-05-28 10:18 UTC (19+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed "
[libre-riscv-dev] [Bug 324] New: create POWER9 DIV pipeline
2020-05-28 10:03 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline "
[libre-riscv-dev] [Bug 323] New: create POWER9 MUL pipeline
2020-05-27 22:21 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline "
[libre-riscv-dev] Power ISA v3.1 bug - parityw
2020-05-27 22:09 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw "
[libre-riscv-dev] [Bug 355] New: game theory "state" packet engine needed
2020-05-27 21:42 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 355] game theory "state" packet engine needed "
[libre-riscv-dev] daily kan-ban update 27may2020
2020-05-27 18:42 UTC (4+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 305] New: Create Pipelined ALU similar to alu_hier.py
2020-05-27 18:38 UTC (7+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py "
[libre-riscv-dev] [Bug 348] New: POWER9 SPR pipeline needed
2020-05-27 17:58 UTC (5+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed "
[libre-riscv-dev] [Bug 325] New: create POWER9 TRAP pipeline
2020-05-27 14:49 UTC (7+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline "
[libre-riscv-dev] [Bug 343] New: compalu_multi write requests need to hook into Data.ok
2020-05-27 14:27 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok "
[libre-riscv-dev] [Bug 340] New: formal proof of POWER9 SHIFTROT pipeline needed
2020-05-27 14:21 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed "
[libre-riscv-dev] [Bug 332] New: Formal correctness proof needed for CR pipeline
2020-05-27 14:09 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline "
[libre-riscv-dev] [Bug 306] New: Formal Correctness Proof for ALU pipeline
2020-05-27 14:06 UTC (5+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline "
[libre-riscv-dev] POWER9 formal correctness proofs collaboration
2020-05-27 13:12 UTC - mbox.gz / Atom
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
2020-05-27 11:10 UTC (6+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 354] New: idea/optimisation: make FP CMP also do INT CMP
2020-05-27 0:46 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 354] idea/optimisation: make FP CMP also do INT CMP "
[libre-riscv-dev] [Bug 345] New: define POWER9 regfiles
2020-05-27 0:41 UTC (3+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 345] define POWER9 regfiles "
[libre-riscv-dev] [Bug 351] New: create a "block" (mass) regfile port (read and write) onto an array-based regfile
2020-05-26 23:20 UTC (15+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile "
[libre-riscv-dev] funny article about Rust and technical interviews
2020-05-26 22:24 UTC (4+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC
2020-05-26 21:30 UTC (4+ messages) - mbox.gz / Atom
[libre-riscv-dev] daily kan-ban update 26may2020
2020-05-26 20:00 UTC (17+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 342] New: formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
2020-05-26 17:52 UTC (10+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed "
[libre-riscv-dev] [Bug 336] New: add indicator to Decode2ExecuteType that RA is zero
2020-05-26 17:22 UTC (30+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
[libre-riscv-dev] daily kan-ban update 25may2020
2020-05-26 0:11 UTC (16+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 337] New: Convention for register outputs in *OutputData structures is to use "Data"
2020-05-25 22:53 UTC (3+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 337] Convention for register outputs in *OutputData structures is to use "Data" "
[libre-riscv-dev] [Bug 316] New: bperm TODO
2020-05-25 21:36 UTC (7+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 316] bperm TODO "
[libre-riscv-dev] [Bug 352] New: virtual (dependency-tracked) regfile needed
2020-05-25 14:23 UTC - mbox.gz / Atom
[libre-riscv-dev] [Bug 350] New: LDSTCompUnit also needs to support zeroing on RA
2020-05-25 11:57 UTC (6+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA "
[libre-riscv-dev] [Bug 335] New: Formal Correctness Proof for Branch pipeline
2020-05-25 0:22 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline "
[libre-riscv-dev] [Bug 318] New: fix LDSTCompUnit
2020-05-25 0:14 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 318] fix LDSTCompUnit "
[libre-riscv-dev] [Bug 349] New: privileged-instruction decoding function needed
2020-05-24 21:51 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 349] privileged-instruction decoding function needed "
[libre-riscv-dev] [Bug 333] New: investigate why CR pipeline code took 100% CPU and locked up generating ILANG
2020-05-24 20:48 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG "
[libre-riscv-dev] [Bug 314] New: Create Condition Register pipeline
2020-05-24 20:47 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline "
[libre-riscv-dev] [Bug 347] New: add setb (to CR pipeline?)
2020-05-24 19:57 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 347] add setb (to CR pipeline?) "
[libre-riscv-dev] daily kan-ban update 24may2020
2020-05-24 19:30 UTC (3+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 331] New: Formal Correctness Proof for LOGICAL pipeline
2020-05-24 19:25 UTC (3+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline "
[libre-riscv-dev] [Bug 197] Formal correctness proof needed of the 6600-style Out-of-Order execution engine
2020-05-24 18:24 UTC - mbox.gz / Atom
[libre-riscv-dev] [Bug 346] New: simplified test link between compunits and regfile
2020-05-24 15:33 UTC - mbox.gz / Atom
[libre-riscv-dev] idea for testing pipelines
2020-05-24 15:30 UTC - mbox.gz / Atom
[libre-riscv-dev] [Bug 344] New: missing mtmsr and mfsprd
2020-05-24 14:27 UTC - mbox.gz / Atom
page: next prev latest
Libre RISC-V Mailing list Archives (accessible via public-inbox)
Archives are clonable: git clone --mirror https://inbox.libre-soc.org/libre-riscv-dev
Example config snippet for mirrors
AGPL code for this site: git clone https://public-inbox.org/public-inbox.git