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From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 15jun2020
Date: Mon, 15 Jun 2020 16:03:52 -0400
Message-ID: <A3CC338E-A1BB-46A6-8347-760CA3881DBD@gatech.edu> (raw)
In-Reply-To: <CAPweEDx1hevEgNrMvEdORv3cLmFyBqgrA4eAK5Z4Vuo0f=SqcA@mail.gmail.com>

> 
> what i might do for now is just drop in a small SRAM just to get
> something working.

You might already know, but you can do an SRAM like so:
**should also map to ECP5 BRAM blocks in Yosys

```
from nmigen import Memory
gprf = Memory(width=32, depth=32)
gprf_rp1 = gprf.read_port()
gprf_rp2 = gprf.read_port()
gprf_wp  = gprf.write_port()
```

https://github.com/lambdaconcept/minerva/blob/master/minerva/core.py#L227

Yehowshua
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  reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-15 15:11 Luke Kenneth Casson Leighton
2020-06-15 19:58 ` Luke Kenneth Casson Leighton
2020-06-15 20:03   ` Yehowshua [this message]
2020-06-15 21:12     ` Cole Poirier
2020-06-15 21:21       ` Luke Kenneth Casson Leighton
2020-06-15 21:20     ` Luke Kenneth Casson Leighton
2020-06-16  3:08 ` Jacob Lifshay
2020-06-16 10:52   ` Luke Kenneth Casson Leighton

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