[libre-riscv-dev] daily kan-ban update 15jun2020

[Luke Kenneth Casson Leighton <lkcl@lkcl.net>]

yesterday:

* sorted byte-reversal issue in LD/ST sim code, matched against qemu,
sorted the hardware to match (including lbrrx)
* added budgets to the NLNet Wishbone Grant which cover documentation
and the POWER9 core.
* added a new list libre-soc-bugs and moved bugzilla-daemon to report
all bugreports to that new list (*not* libre-riscv-dev)
* investigated and tracked down a wishbone SRAM slave that will help
us do testing.

today:

* added in the LD/ST unit tests into test_core.py and disabled them
pending an investigation into why the LDSTCompUnit remains "busy"
after the 1st instruction.

rest of day:

* look at why the 2nd LD/ST instruction remains "busy" in test_core.py
where in the test_ldst_compunit.py it is fine
* if that's found quickly, continue investigating the next step which
is to first add in an instruction "reader" (I-Cache path) and second
to point the PC at it and actually get instructions from an actual
I-Cache / SRAM.

with so many unit tests demonstrating functionally correct behaviour
of the various instructions (corner-cases notwithstanding) i should
have actual basic program execution pretty much straight away.

l.

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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