[libre-riscv-dev] daily kan-ban update 15jun2020

[libre-riscv-dev] daily kan-ban update 15jun2020

[Luke Kenneth Casson Leighton]

yesterday:

* sorted byte-reversal issue in LD/ST sim code, matched against qemu,
sorted the hardware to match (including lbrrx)
* added budgets to the NLNet Wishbone Grant which cover documentation
and the POWER9 core.
* added a new list libre-soc-bugs and moved bugzilla-daemon to report
all bugreports to that new list (*not* libre-riscv-dev)
* investigated and tracked down a wishbone SRAM slave that will help
us do testing.

today:

* added in the LD/ST unit tests into test_core.py and disabled them
pending an investigation into why the LDSTCompUnit remains "busy"
after the 1st instruction.

rest of day:

* look at why the 2nd LD/ST instruction remains "busy" in test_core.py
where in the test_ldst_compunit.py it is fine
* if that's found quickly, continue investigating the next step which
is to first add in an instruction "reader" (I-Cache path) and second
to point the PC at it and actually get instructions from an actual
I-Cache / SRAM.

with so many unit tests demonstrating functionally correct behaviour
of the various instructions (corner-cases notwithstanding) i should
have actual basic program execution pretty much straight away.

l.

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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Re: [libre-riscv-dev] daily kan-ban update 15jun2020

[Luke Kenneth Casson Leighton]

On Mon, Jun 15, 2020 at 4:11 PM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:

> * look at why the 2nd LD/ST instruction remains "busy" in test_core.py
> where in the test_ldst_compunit.py it is fine

found it quickly.  turns out that you must not link signals together
*after* you create a nmigen Simulator instance.  the nmigen
Simulator(m) instance must be the last thing done.

now the LD/ST unit tests also work in test_core.py as well.  this is a
significant step because with LD/ST, branch, and add (etc.) all
confirmed working, simple loops can be created once we have
instruction read/feed in place.

> * if that's found quickly, continue investigating the next step which
> is to first add in an instruction "reader" (I-Cache path) and second
> to point the PC at it and actually get instructions from an actual
> I-Cache / SRAM.

this is now the next high priority task: getting an SRAM that's on the
other side of a wishbone bus operational (and properly unit tested)
then dropping it into place on the L0CacheBuffer.

on a separate path an instruction queue can also be added... however
agaaain, that needs to be reading from a Memory, preferably via a
wishbone interface.

what i might do for now is just drop in a small SRAM just to get
something working.

l.

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Re: [libre-riscv-dev] daily kan-ban update 15jun2020

[Yehowshua]

> 
> what i might do for now is just drop in a small SRAM just to get
> something working.

You might already know, but you can do an SRAM like so:
**should also map to ECP5 BRAM blocks in Yosys

```
from nmigen import Memory
gprf = Memory(width=32, depth=32)
gprf_rp1 = gprf.read_port()
gprf_rp2 = gprf.read_port()
gprf_wp  = gprf.write_port()
```

https://github.com/lambdaconcept/minerva/blob/master/minerva/core.py#L227

Yehowshua
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Re: [libre-riscv-dev] daily kan-ban update 15jun2020

[Cole Poirier]

Yesterday: Mostly processing the huge list of todos I generated over my
3 hour convo with Luke on Saturday, as well as running some errands.

Today: 

On boarding two new project members (my two sisters hehe)

Talking with Dan Leighton (Luke's brother) about Elm

Start organizing my todo list for myself, which includes figuring out
how to organize the project 'todo list' and bug tracking,
budget/timeline tracking, roadmap etc. My personal to do list will be
done on a private online Kanban-like service, which I will use to
organize myself enough that I can start putting all of the project
related todos into my wiki page or elsewhere. Will be discussing what
I'm doing on Libre-SOC Org bug reports, but keeping my private 'to do'
list duplicated in the private kanban app so I can organize myself
visually. I will end up cloning something like this, with significant
improvements for the Elm application that I will be deveopling with Dan
and Anais over the next couple months. Then I will no longer maintain
this private to do list as I will prefer using our augmented to our
needs kanban-like application.

Going through every diagram on the wiki and picking out the most basic,
legible ones for Elle to start turning into SVGs.

Doing Robert Baruch's nmigen tutorial with anais

Tomorrow:

Continuing much of the above

Starting to write the bpermd HDL tutorial as I work through it with Anais


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Re: [libre-riscv-dev] daily kan-ban update 15jun2020

[Luke Kenneth Casson Leighton]

---
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On Mon, Jun 15, 2020 at 9:04 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> >
> > what i might do for now is just drop in a small SRAM just to get
> > something working.
>
> You might already know, but you can do an SRAM like so:

yes - been using that as part of a semi-integrated thing in TstL0CacheBuffer:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/l0_cache.py;hb=HEAD#l507

which in turn uses TestMemory:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/testmem.py;hb=HEAD

which in turn uses nmigen Memory

l.

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Re: [libre-riscv-dev] daily kan-ban update 15jun2020

[Luke Kenneth Casson Leighton]

On Mon, Jun 15, 2020 at 10:12 PM Cole Poirier <colepoirier@gmail.com> wrote:
>
> Yesterday: Mostly processing the huge list of todos I generated over my
> 3 hour convo with Luke on Saturday, as well as running some errands.

:)

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Re: [libre-riscv-dev] daily kan-ban update 15jun2020

[Jacob Lifshay]

planning on working on the div pipeline today, many other things have
distracted from that.

Jacob

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Re: [libre-riscv-dev] daily kan-ban update 15jun2020

[Luke Kenneth Casson Leighton]

On Tue, Jun 16, 2020 at 4:09 AM Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> planning on working on the div pipeline today, many other things have
> distracted from that.

i hear ya :)

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