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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 15jun2020
Date: Mon, 15 Jun 2020 22:20:48 +0100
Message-ID: <CAPweEDwMCQswiy84wBude8QYOJeu77CSp39rTkGhGvLWxqnfJA@mail.gmail.com> (raw)
In-Reply-To: <A3CC338E-A1BB-46A6-8347-760CA3881DBD@gatech.edu>

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Jun 15, 2020 at 9:04 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> >
> > what i might do for now is just drop in a small SRAM just to get
> > something working.
>
> You might already know, but you can do an SRAM like so:

yes - been using that as part of a semi-integrated thing in TstL0CacheBuffer:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/l0_cache.py;hb=HEAD#l507

which in turn uses TestMemory:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/testmem.py;hb=HEAD

which in turn uses nmigen Memory

l.

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  parent reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-15 15:11 Luke Kenneth Casson Leighton
2020-06-15 19:58 ` Luke Kenneth Casson Leighton
2020-06-15 20:03   ` Yehowshua
2020-06-15 21:12     ` Cole Poirier
2020-06-15 21:21       ` Luke Kenneth Casson Leighton
2020-06-15 21:20     ` Luke Kenneth Casson Leighton [this message]
2020-06-16  3:08 ` Jacob Lifshay
2020-06-16 10:52   ` Luke Kenneth Casson Leighton

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